Benchmarks "Time to retire our benchmarks" -- Rob Aitken, 2010 ITC'02 SOC Test Benchmarks
  CAD Benchmarking Laboratory (CBL) at North Carolina State University High Level Synthesis Resources at UCSB Advanced EDA Benchmark Datasets
SoftwareLinks to CAD: Free/Shareware Software
Links to CAD: Commercial Software HITEC/PROOFS: A Sequential Circuit Test Generation and Fault Simulation Package CAD Software at University of California, Berkeley CAD Software at Stanford University SREEP (Shift Register Equivalents Enumeration and Synthesis Program) |