[http://ats07.ict.ac.cn/]

------------------------------------------------------------------------
CALL FOR PAPERS

The Sixteenth Asian Test Symposium
October 9-11, 2007, Beijing Friendship Hotel, Beijing, P.R.China


Sponsored by
IEEE Computer Society
Test Technology Technical Council
Institute of Computing Technology, CAS
In cooperation with
Technical Committee on Fault Tolerant Computing 
China Computer Federation

SCOPE
The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the World, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. 
Topics of interest include, but are not limited to:


SUBMISSIONS
Regular session: Original technical papers on the above topics are invited. Paper submissions should be complete manuscripts, not extending six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, fax number, and e-mail address of the contact author. A 50-words abstract and five keywords are also required. 
All submissions are to be made electronically through the ATS’07 website. Detailed instructions for submissions are to be found at the ATS’07 website. Electronic submissions (PDF or PS files) are strongly recommended. 
The submission will be considered evidence that upon acceptance the author(s) will prepare the final manuscript (6 pages for regular session) in time for inclusion in the proceedings and will present the paper at the Symposium.
Industry session: This session will address a wide range of practical problems in LSI test, board and system test, diagnosis, failure analysis, design verification, and so on. A one-page abstract is required for submission. Each submission should also include the complete address and designate a contact person and a presenter. Abstract submissions should be emailed to Industrial Arrangement Chair ([email protected]).

KEY DATES                  
Submission deadline: April 1, 2007 (Regular session); May 12, 2007 (Industry session)
Notification of acceptance: May 31, 2007
Camera-ready copy: June 29, 2007
Symposium: October 9-11, 2007

General Co-Chair(s)
Xiaowei Li
Institute of Computing Technology, CAS

Kwang-Ting (Tim) Cheng
University of California at Santa Barbara

Program Co-Chair(s)
Huawei Li
Institute of Computing Technology, CAS

Xiaoqing Wen
Kyushu Institute of Technology

Tutorial Chair
Huaguo Liang
He Fei University of Technology

Publicity Chair
Yinhe Han
Institute of Computing Technology, CAS

Publication Chair
Yu Hu
Institute of Computing Technology, CAS

Finance Chair
Yongjun Xu
Institute of Computing Technology, CAS

Local Arrangement Chair
Rong Zhang
Institute of Computing Technology, CAS

Registration Chair
Tao Lv
Institute of Computing Technology, CAS

Industrial Arrangement Chair 
Anis Uzzaman
Cadence Encounter Test Group, New York

North American Liaison
Alex Orailoglu
University of California at San Diego

European Liaison
Zebo Peng
Linkoping University


FURTHER INFORMATION
Email: [email protected]
URL: http://ats07.ict.ac.cn

Program Committee
V. D. Agrawal
J. Bian
K. Chakrabarty
T.-Y. Chang 
X. Chen
K.-T. Cheng
D. R. Chowdhury
D. K. Das
P. Girard
Z. Guo
Y. Gong
S. K. Gupta 
M. Hashizume
K. Hatayama 
T. Hayashi
Y. He
H. Hiraishi 
M. S. Hsiao
Y. Hu
C.-T. Huang
Y. Gong
S. K. Gupta 
M. Hashizume
K. Hatayama 
T. Hayashi
Y. He
H. Hiraishi 
M. S. Hsiao
Y. Hu
C.-T. Huang
C.-L. Lee 
K.-J. Lee 
C.-M. J. Li
C. Liu
H. Liang
Z. Luo
M. R. Lyu
E. J. Marinissen
Y. Min
S. Mitra
F. Muradali
N. Nicolici
S. Ohtake
P. Pande
S. Patil 
Z. Peng
I. Polian
S. Reddy
M. Renovell
J. Rivoir 
K. K. Saluja
I. Sengupta
L. Shen
P. Song
X. Song
Y. Sun
H. Takahashi 
N. A. Touba 
A. Uzzaman
S.-J. Wang
C.-W. Wu
H.-J. Wunderlich
D. Xiang 
L. Xiao
Q. Xu
S. Xu
J. Yang
D. Zhao
R. Zhao



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Final Program

Monday, October 8, 2007

09:00
to
12:00

Tutorial 1
DFX: The Convergence of Yield, Manufacturing, and Test
Robert Aitken (ARM, USA)
14:00
to
17:00
Tutorial 2
Understanding failure mechanisms and test methods in nanometer technologies
Jaume Segura (University of Illes Balears, Spain) 
Charles Hawkins (University of New Mexico, USA)

18:30
to
21:00
Reception (Ballroom, Building 1)

Tuesday, October 9, 2007
08:30
to
12:00
Opening Session

8:30-9:00 Plenary Opening
9:00-9:45 Keynote Speech 1: New Paths for Test
Jacob Abraham (University of Texas at Austin - USA)
9:45-10:30 Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test
Sanjiv Taneja (Cadence Design Systems - USA)
10:30-11:00 Invited Talk 1: Testing of Power Constraint Computing
T. M. Mak (Intel Corporation - USA)
11:00-11::30 Invited Talk 2: EDA to the Rescue of the Silicon Roadmap
T. W. Williams (Synopsys - USA)
11:30-12:00 Invited Talk 3: Foundry full-scale reliability testing capability setup for advanced technology
Kary Chien (Semiconductor Manufacturing International (Shanghai) Corp. - China

13:30
to
14:45

Session 2 A-Fault Modeling and Functional Test
Session Chair: S. M. Reddy (Univ. of Iowa, USA)

- 146) The Region-Exhaustive Fault Model,
Abhijit Jas (Intel Corporation - USA), Suriyaprakash Natarajan (Intel Corporation - USA), Srinivas Patil (Intel Corporation - USA)

- 148) Mining Sequential Constraints for Pseudo-Functional Testing,
Weixin Wu (Virginia Tech. - USA), Michael S. Hsiao (Virginia Tech - USA)

- 3) Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation,
Irith Pomeranz (Purdue University - USA), Praveen K. Parvathala (Intel Corporation - USA), Srinivas Patil (Intel Corporation - USA)

Session 2 B-Fault Diagnosis I
Session Chair: B. Keller (Cadence, USA)

- 82) Fast Bridging Fault Diagnosis using Logic Information,
Alexandre Rousset (LIRMM - France), Alberto Bosio (LIRMM - France), Patrick Girard (LIRMM - France) , Christian Landrault (LIRMM - France), Serge Pravossoudovitch (LIRMM - France), Arnaud Virazel (LIRMM - France)

- 50) Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines,
Hiroshi Takahashi (Ehime University - Japan), Yoshinobu Higami (Ehime University - Japan), Shuhei Kadoyama(Ehime University - Japan) , Takashi Aikyo (Ehime University - Japan) , Yuzo Takamatsu (Ehime University - Japan) , Koji Yamazaki (Meiji University - Japan), Toshiyuki Tsutsumi (Meiji University - Japan), Hiroyuki Yotsuyanagi (Tokushim University - Japan), Masaki Hashizume(the University of Tokushim - Japan)

- 144) Fault Dictionary Based Scan Chain Failure Diagnosis,
Ruifeng Guo (Mentor Graphics Corporation - USA), Yu Huang (Mentor Graphics Corporation - USA), Wu-Tung Cheng (Mentor Graphics Corporation - USA)

Session 2 C-Panel 1: Test Education In Global Economy

Organizer: Tim Cheng (Univ. of California, Santa Barbara, USA)
Moderator: Tim Cheng( Univ. of California, Santa Barbara, USA)
Panelists: 
Jacob Abraham (Univ. of Texas, Austin, USA) 
Greg Jordan (Cisco Systems, USA) 
Salvador Mir (TIMA, France)
Yinghua Min (Institute of Computing Technology, Chinese Academy of Sciences, China)
Jeremy Wang (Fabless Semiconductor Association, Asia Pacific)
Cheng-Wen Wu (National TsingHua University, Taiwan)

15:15
to
16:40

Session 3 A-Delay Test I
Session Chair: T. Aikyo (STARC, Japan)

- 91) Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults,
Shahdad Irajpour (University of Southern California - USA), Sandeep K. Gupta (University of Southern California - USA), Melvin A. Breuer (University of Southern California - USA)

- 31s) False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults,
Yuki Yoshikawa (Hiroshima City University - Japan), Satoshi Ohtake (Nara Institute of Science and Technology - Japan), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

- 155s) Using Programmable On-Product Clock Generation (OPCG) for Delay Test,
Brion Keller (Cadence Design Systems Inc. - USA), Anis Uzzaman (Cadence Design Systems, Inc. - USA), Bibo Li (Cadence Design Systems, Inc. - USA), Tom Snethen (Cadence Design Systems, Inc. - USA)

- 96s) An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits,
Shaahin Hessabi (Sharif University of Technology - Iran) Elham Khayat Moghaddam (Sharif University of Technology - Iran)

Session 3 B-Test Compression
Session Chair:K.-J. Lee (Cheng-Kung Univ., Taiwan)

- 25) A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding,
Seongmoon Wang (NEC Labs America - USA), Wenlong Wei (NEC Labs America - USA), Srimat T. Chakradhar (NEC Labs America -USA)

127s) Test Compression / Decompression Based on JPEG VLC Algorithm,
Hideyuki Ichihara (Hiroshima City University - Japan), Yukinori Setohara (Hiroshima City University - Japan), Yusuke Nakashima (Hiroshima City University - Japan), Tomoo Inoue (Hiroshima City University - Japan)

151s) A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition,
Aiman H.El-Maleh (King Fahd University of Petroleum&Minerals - Saudi Arabia), Mustafa Imran Ali (King Fahd Unversity of Petroleum&Minerals - Saudi Arabia), Ahmad A.Al-Yamani (King Fahd University of Petroleum &Minerals - Saudi Arabia)

121s) Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,
Sying-Jyan Wang (National Chung-Hsing University - Taiwan), Po-Chang Tsai (National Chung-Hsing University - Taiwan), Hung-Ming Weng (National Chung-Hsing University - Taiwan ), Katherine Shu-Min Li (National Sun Yat-Sen University - Taiwan)

Session 3 C-Power Aware Test I
Session Chair: P. Girard (LIRMM, France)

- 110) Resistive Bridging Faults DFT with Adaptive Power Management Awareness,
Urban Ingelsson (University of Southampton - United Kingdom), Paul Rosinger (University of Southampton - United Kingdom), S. Saqib Khursheed (University of Southampton - United Kingdom), Bashir M Al-Hashimi (University of Southampton - United Kingdom), Peter Harrod (ARM Limited - United Kingdom)

- 105s) Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE,
Dan Zhao (University of Louisiana at Lafayette - USA), Ronghua Huang (University of Louisiana at Lafayette - USA), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

-160s) An Efficient Peak Power Reduction Technique for Scan Testing,
Meng-Fan Wu (National Taiwan University - Taiwan), Kai-Shun Hu (National Taiwan University - Taiwan), Jiun-Lang Huang (National Taiwan University - Taiwan)

-27s) High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects,
Sunghoon Chun (Yonsei University - Korea), Yongjoon Kim (Yonsei University - Korea), Sungho Kang (Yonsei University - Korea)

17:10
to
18:15

Session 4 A-DFT I
Session Chair: P. Song (IBM, USA)
(17:10 ~ 18:10)

- 89s) A RTL Testability Analyzer Based on Logical Virtual Prototyping,
Yu Huang(Mentor Graphics Corporation - USA), Nilanjan Mukherjee (Mentor Graphics Corporation - USA), Wu-Tung Cheng (Mentor Graphics Corporation - USA), Greg Aldrich (Mentor Graphics Corporation - USA)

- 125s) Optimum Test Set for Bridging Faults Detection in Reversible Circuits,
Hafizur Rahaman (Bengal Engg. and Science University - India), Dipak K. Kole (Bengal Engg. and Science University - India), Debesh K. Das (Jadavpur University - India), Bhargab B. Bhattacharya (Indian Statistical Institute - India)

- 132s) Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,
Sying-Jyan Wang (National Chung-Hsing University - Taiwan), Xin-Long Li (National Chung-Hsing University - Taiwan), Katherine Shu-Min Li (National Sun Yat-Sen University - Taiwan)

Session 4 B- RF Test
Session Chair: S. Mir (TIMA, France)
(17:10 ~ 18:10)

- 60s) A Test and Diagnosis Methodology for RF Transceivers,
Hung-Kai Chen (National Chiao Tung University - Taiwan), Chauchin Su (National Chiao Tung University - Taiwan)

- 114s) Fourier Spectrum-Based SignatureTest: A Genetic CAD Toolbox for Reliable RF Testing Using Low-Performance Test Resources,
Ganesh Srinivasan(Texas Instruments Inc. - USA), Abhijit Chatterjee (Georgia Institute of Technology - USA), Vishwanath Natarajan (Georgia Institute of Technology - USA)

- 12s) A BIST Technique for RF Voltage-Controlled Oscillators,
Hsieh-Hung Hsieh (National Taiwan University - Taiwan ), Yen-Chih Huang (National Taiwan University - Taiwan), Liang-Hung Lu (National Taiwan University - Taiwan), Guo-Wei Huang(National Nano Device Laboratories - Taiwan)

Session 4 C-Software Test 
Session Chair: M. Hsiao (Virginia Tech., USA)

- 133) A Improved Test Case Generation Method of Pair-Wise Testing,
Feng-An Qian(Tongji University - China), Jian-hui Jiang (Tongji University - China)

- 41s) System Testing using UML Models,
Monalisa Sarma (Indian Institute of Technology, Kharagpur - India), Rajib Mall (Indian Institute of Technology, Kharagpur - India)

- 80s) Reconsideration of Software Reliability Measurements,
Shiyi Xu (Shanghai University - China)

------------------------------------
Wednesday, October 10, 2007

08:30
to
09:45

Session 5 A-Design Verification
Session Chair: K. Furuya (Chuo Univ., Japan)

- 95) An Accurate Analysis of Microprocessor Design Verification, 
Haihua Shen (Institute of Computing Technology, Chinese Academy of Sciences - China), Heng Zhang (Institute of Computing Technology, Chinese Academy of Sciences - China)

- 61) Optimized Assignment Coverage Computation in Formal Verification of Digital Systems, 
Majid Nabi (Tehran University - Iran), Hamid Shojaei (Tehran University - Iran), Zainalabedin Navabi (Tehran University - Iran)

- 123) EHSAT Modeling from Algorithm Description for RTL Model Checking, 
Xiaoqing Yang (Tsinghua University - China), Jinian Bian (Tsinghua University - China), Shujun Deng (Tsinghua University - China), Yanni Zhao (Tsinghua University - China)

Session 5 B- SOC Test
Session Chair: I. Polian (Albert-Ludwigs Univ., Germany)

 33) Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip,
Thomas Edison Yu (Nara Institute of Science and Technology - Japan), Tomokazu Yoneda (Nara Institute of Science and Technology - Japan), Krishnendu Chakrabarty (Duke University - USA), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

- 97) Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC,
Jaehoon Song (Hanyang University - Korea), Juhee Han (Hanyang University - Korea), Dooyoung Kim (Hanyang University - Korea), Hyunbean Yi (Hanyang University - Korea), Sungju Park (Hanyang University - Korea)

- 22) Test Scheduling for Memory Cores with Built-In Self-Repair,
Tomokazu Yoneda (Nara Institute of Science and Technology - Japan), Yuusuke Fukuda (Nara Institute of Science and Technology - Japan), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

Session 5 C-Panel 2: Next generation Test, Diagnostics and Yield challenges for EDA, ATE, IP and Fab - A Perspective from all sides

Organizer: Anis Uzzaman (Cadence Design Systems, USA)
Moderator: Brion Keller (Cadence Design Systems, USA)
Panelists: 
Robert Aitken (ARM, USA)
Wu-Tung Cheng (Mentor Graphics, USA)
Yasuharu Kohiyama (Advantest, Japan)
C. P. Ravikumar (Texas Instrument, India)
Yasuo Sato (Hitachi, Japan)

10:15
to
11:30

Session 6 A-Industry
Session Chair: A. Uzzaman (Cadence, USA)

Industry-03) I DDQ Test Challenges in Nanotechnologies:A Manufacturing Test Strategy,
Yu Wei P'ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong (Marvell Semiconductor, Malaysia)

Industry-05) Experimental Results of Transition Fault Simulation with DC Scan Tests,
Wataru Kawamura, Takeshi Onodera (Sony Corporation, Japan)

Industry-06) A Review of Power Strategies for DFT and ATPG,
Brion Keller, Tom Jackson and Anis Uzzaman (Cadence Design Systems, Inc., USA)

Industry-07) Concurrent Test Implementations,
Shawn Molavi, Toby McPheeters (Broadcom Corporation, USA)

Industry - 09) Scan Diagnosis and Its Successful Industrial Applications-- Yield Improvement, Verified Flow, Accuracy, Layout Aware and Volume Diagnosis,
Wu Yang, Wu-tung Cheng, Martin Keim, Yu Huang and Randy Klingenberg (Mentor Graphics Corporation, USA)

ession 6 B- Analog Test
Session Chair: J.-L. Huang (Taiwan Univ., Taiwan)

- 73) A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement, 
Nai-Chen Daniel Cheng (Industrial Technology Research Institute - Taiwan), Yu Lee(Industrial Technology Research Institute - Taiwan), Ji-Jan Chen(Industrial Technology Research Institute - Taiwan)

- 161) An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing,
Dongwoo Hong (University of California, Santa Barbara - USA), Kwang-Ting Cheng (University of California, Santa Barbara - USA)

- 11) Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods,
Xinsong Zhang (University of Arkansas - USA), Simon S. Ang (University of Arkansas - USA), Chandra Carter (Texas Instruments - USA)

Session 6 C-Power Aware Test II
Session Chair: C.P. Ravikumar (TI, India)

- 122) Impact of Simultaneous Switching Noise on the Static Behavior of Digital CMOS Circuits, 
Florence Azais (LIRMM - CNRS / University of Montpellier - France) , Laurent Larguier (LIRMM - CNRS / University of Montpellier - France), Michel Renovell (LIRMM - CNRS / University of Montpellier - France)

- 14) Effect of IR-Drop on Path Delay Testing Using Statistical Analysis,
Chunsheng Liu (Nebraska-Lincoln University - USA) , Yang Wu (Nebraska-Lincoln University - USA), Yu Huang (Mentor Graphics Corporation - USA)

- 166) Low Power Reduced Pin Count Test Methodology,
Krishna Chakravadhanula (Cadence Design Systems - USA), Nitin Parimi (Cadence Design Systems - USA), Brian Foutz (Cadence Design Systems - USA), Bing Li (Cadence Design Systems - USA), Vivek Chickermane (Cadence Design Systems - USA)

13:30
to
15:05

Session 7 A-Test Generation I 
Session Chair: M. Renovell (LIRMM, France)
(13:30 ~ 15:00)

- 53) Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects,
Minjin Zhang (Institute of Computing, Technology, Chinese Academy of Sciences - China), Xiaowei Li (Institute of Computing Technology, Chinese Academy of Sciences - China)

- 76) Simulating Open-Via Defects,
Stefan Spinner (Albert-Ludwigs-University - Germany), Jie Jiang (Albert-Ludwigs-University - Germany), Ilia Polian (Albert-Ludwigs-University - Germany), Piet Engelke (Albert-Ludwigs-University - Germany), Bernd Becker (Albert-Ludwigs-University - Germany)

- 40s) Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator,
Yoshinobu Higami (Ehime University - Japan), Kewal K.Saluja (University of Wisconsin - Madison - USA), Hiroshi Takahashi (Ehime University - Japan), Shin-ya Kobayashi (Ehime University - Japan ), Yuzo Takamatsu (Ehime University - Japan )

- 108s) Fault-dependent/independent Test generation Methods for State Observable FSMs,
Toshinori Hosokawa (Nihon University - Japan), Ryoichi Inoue (Nihon University - Japan ), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

Session 7 B- Fault Diagnosis II
Session Chair: S. Patil (Intel, USA)

- 94) Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead,
Huaxing Tang (Mentor Graphics Corporation - USA), Chen Liu (University of Iowa - USA ), Wu-Tung Cheng (Mentor Graphics Corporation - USA), Sudahkar M. Reddy (University of Iowa - USA), Wei Zou (Mentor Graphics Corporation - USA)

- 164) An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability,
Feijun Zheng (Zhejiang University - China), Kwang-Ting Cheng (California University -USA), Xiaolang Yan(Zhejiang University - China), John Moondanos(Intel Corporation), Ziyad Hanna(Intel Corporation)

- 90) Programmable Logic BIST for At-speed Test,
Yu Huang (Mentor Graphics Corporation - USA), Xijiang Lin (Mentor Graphics Corporation - USA)

- 1s) Diagnostic Test Generation Targeting Equivalence Classes,
Irith Pomeranz (Purdue University - USA), Sudhakar M. Reddy (University of Lowa - USA)

Session 7 C-Soft Error Issue
Session Chair: M. Inoue (NAIST, Japan)
(13:30 ~ 15:00)

- 118) Improving Circuit Robustness With Cost-Effective Soft-Error-Tolerant Sequential Elements,
Mingjing Chen (University of California - USA), Alex Orailoglu (University of California - USA)

- 8) CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors,
Shijian Zhang (Institute of Computing Technology, Chinese Academy of Sciences - China), Weiwu Hu (Institute of Computing Technology, Chinese Academy of Sciences - China)

- 167s) Monitoring Transient Errors in Sequential Circuits,
Ramashis Das (University of Michigan - USA), John P. Hayes (University of Michigan - USA)

- 139s) Frequency Analysis Model for Propagation of Transient Errors in Combinational Logic,
Shaohua Lei(Institute of Computing Technology, Chinese Academy of Sciences - China), Yinhe Han(Institute of Computing Technology, Chinese Academy of Sciences - China), Xiaowei Li(Institute of Computing Technology, Chinese Academy of Sciences - China)

15:10
to
18:30
Social event (The Summer Palace)

18:30
to
22:00
Banquet (Imperial Tingli Hall Restaurant, at the Summer Palace)

-----------------------------------------
Thursday, October 11, 2007

08:30
to
09:45

Session 8 A-DFT II
Session Chair: X. Gu (Cisco, USA)

- 13) Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost, 
Dong Xiang (Tsinghua University - China), Krishnendu Chakrabarty (Duke University - USA), Dianwei Hu (Tsinghua University - China), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

- 163) Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan, 
Gefu Xu(Auburn University - USA), Adit D. Singh (Auburn University - USA)

- 101) An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing, 
Xiaoxin Fan (Institute of Computing, Technology, Chinese Academy of Sciences - China), Yu Hu (Institute of Computing Technology, Chinese Academy of Sciences - China), Laung-Terng Wang (Syntest, Inc. - USA)

Session 8 B- Memory Test I
Session Chair: S. Gupta (Univ. of Southern California, USA)
(08:30 ~ 09:40)

- 138) A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories,
Li-Ming Denq (National Tsing Hua University - Taiwan), Cheng-Wen Wu (National Tsing Hua University - Taiwan)

- 115) CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs,
Hsiang-Huang Wu (Realtek Semiconductor Corporation - Taiwan), Jin-Fu Li(National Central University -Taiwan), Chi-Feng Wu(National Tsing Hua University -Taiwan), Cheng-Wen Wu(National Tsing Hua University -Taiwan)

- 5s) Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2),
Jochen Rivoir (Verigy Germany GmbH - Germany)

Session 8 C-Panel 3 Test roles in diagnosis and silicon debug
Session Chair: F. Muradali (National Semiconductor, USA)

Organizer: Anis Uzzaman (Cadence Design Systems, USA)
Moderator: Fidel Muradali (National Semiconductor, USA)
Panelists: 
Takashi Aikyo (Fujitsu/STARC, Japan)
Robert Aitken (ARM, USA)
Rajesh Galivanche (Intel, USA)
Tom Jackson (Cadence, USA)
Takeshi Onodera (Sony, Japan)

10:15
to
11:30

Session 9 A-BIST
Session Chair: Z. Peng (Linkoping Univ., Sweden)

- 30) Programmable Scan-Based Logic Built-In Self Test,
Liyang Lai (Mentor Graphics Corporation - USA), Wu-Tung Cheng (Mentor Graphics Corporation - USA), Thomas Rinderknecht (Mentor Graphics Corporation - USA)

- 84) Evaluation of a BIST Technique for CMOS Imagers,
Livier Lizarraga(TIMA Laboratory - France), Salvador Mir (TIMA Laboratory - France), Gilles Sicard (TIMA Laboratory -France )

- 93) Built-In Speed Grading with a Process-Tolerant ADPLL,
Hsuan-Jung Hsu (National Tsing-Hua University, -Taiwan ), Chun-Chieh Tu (National Tsing-Hua University, -Taiwan ), Shi-Yu Huang (National Tsing-Hua University - Taiwan)

Session 9 B- Current Test
Session Chair: Y. He (Hunan Univ., China)

- 169) Testing RF Components with Current Signatures, 
Selim Akbay (Georgia Institute of Technology - USA), Shreyas Sen (Georgia Institute of Technology - USA), Abhijit Chatterjee (Georgia Institute of Technology - USA)

- 106) Current Testable Design of Resistor String DACs,
Masaki Hashizume (Tokushima University - Japan), Yutaka HATA (Tokushima University - Japan), Tomomi Nishida (Tokushima University - Japan ), Hiroyuki Yotsuyanagi (Tokushima University - Japan), Yukiya Miura (Tokyo Metropolitan University. - Japan)

- 156) Implementation of Defect Oriented Testing and ICCQ Testing for Industrial Mixed-Signal IC,
Liquan Fang (NXP Semiconductors - Netherlands), Yang Zhong (RWTH-Aachen University - Germany), Henk Vande Donk (NXP Semiconductors - Netherlands), Yizi Xing (NXP Semiconductors - Netherlands)

Session 9 C-Power Aware Test III
Session Chair: K. Hatayama (STARC, Japan)

- 130) Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs,
Nan-Cheng Lai (National Chung-Hsing University - Taiwan), Sying-Jyan Wang (National Chung-Hsing University - Taiwan)

- 39) Scan Power Reduction Through Scan Architecture Modification and Test Vector Reordering,
Chandan Giri (Inidian Institute of Technology Kharagpur - India), Pradeep Kumar Choudhary (Inidian Institute of Technology Kharagpur - India ), Santanu Chattopadhyay (Inidian Institute of Technology Kharagpur - India )

- 67) Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique,
Bo-Hua Chen (National Taiwan University - Taiwan ), Wei-Chung Kao (National Taiwan University - Taiwan), Bing-Chuan Bai (National Taiwan University - Taiwan), Shyue-Tsong Shen (National Taiwan University - Taiwan), James C.-M. Li (National Taiwan University - Taiwan)

13:30
to
14:55

Session 10 A-Test Generation II
Session Chair: C. Landrault (LIRMM, France)
(13:30 ~ 14:45)

 77) SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges,
Piet Engelke (Albert-Ludwigs-University - Germany), Bettina Braitling (Albert-Ludwigs-University - Germany), Ilia Polian (Albert-Ludwigs-University - Germany), Michel Renovell (LIRMM - France), Bernd Becker (Albert-Ludwigs-University - Germany)

- 158) Symbolic Path Sensitization Analysis and Applications,
Jian Kang (University of Nebraska - USA), Sharad C. Seth (University of Nebraska - USA), Shashank.K. Mehta (Indian Institute of Technology - Indian)

- 70) Improving Test Pattern Compactness in SAT-based ATPG,
Stephan Eggersglu¨ss(University of Bremen - Germany), Rolf Drechsler (University of Bremen - Germany)

Session 10 B- NOC/SOC Test
Session Chair: Q. Xu (The Chinese Univ. of Hong Kong, China)

- 170) An HDL-Based Platform for High Level NoC Switch Testing,
Mahshid Sedghi (University of Tehran - Iran), Armin Alaghi (University of Tehran - Iran), Elnaz Koopahi (University of Tehran - Iran) , Zainalabedin Navabi (University of Tehran - Iran)

- 16s) Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing,
Fawnizu Azmadi Hussin (Nara Institute of Science and Technology - Japan), Tomokazu Yoneda (Nara Institute of Science and Technology - Japan), Hideo Fujiwara (Nara Institute of Science and Technology - Japan)

- 150s) Test Efficiency Analysis and Improvement for SOC Test Platforms,
Tong-Yu Hsieh (National Cheng Kung University - Taiwan), Kuen-Jong Lee (National Cheng Kung University - Taiwan), Jian-Jhih You (National Cheng Kung University - Taiwan )

- 135s) A Scheme of Test Data Compression with Block Marking and Updating Coding for SoC,
Zhang Lei(Hefei University of Technology -China), Huaguo Liang (Hefei University of Technology -China), Wenfa Zhan (Hefei University of Technology -China), Cuiyun Jiang (Hefei University of Technology -China)

Session 10 C-Special Session on Analog Production Test #1
Session Chair:F. Muradali (National Semiconductor, USA) 
(13:30 ~ 14:50)

- APT1.1) Issues Regarding New Product Release in Semiconductor Manufacturing,
Choon-Sang Chew (National Semiconductor)

- APT1.2) How the Noise Floor Affects the Production Yield,
Akinori Maeda (Verigy, Japan)

- APT1.3) Integrated Test Solution for embedded UHF/RF SOC,
Sean Lu (Broadcom Corporation, Irvine, CA), Dee-Won Lee (Verigy Ltd., Irvine, CA)

- APT1.4) Production Test of High Volume Commercial RFIC,
Friedrich Taenzler (Texas Instruments, Dallas)

15:20
to
16:35

Session 11 A-Delay Test II
Session Chair: S. Kajihara (Kyushu Institute of Tech., Japan)

- 2) Enhanced Broadside Testing for Improved Transition Fault Coverage,
Irith Pomeranz (Purdue University - USA), Sudhakar M. Reddy (University of Iowa - USA)

- 152) On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis,
I-De Huang (University of Southern California - USA), Sandeep K. Gupta(University of Southern California - USA)

- 28) Test Generation for Timing Critical Transition Faults,
Xijiang Lin (Mentor Graphics Corporation - USA), Mark Kassab (Mentor Graphics Corporation - USA), Janusz Rajski (Mentor Graphics Corporation - USA)

Session 11 B- Memory Test II
Session Chair: C.-W. Wu (Tsing-Hua Univ., Taiwan)
(15:20 ~ 16:25)

- 162) Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells,
Jin-Fu Li (National Central University - Taiwan)

- 42s) Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior,
Magali Bastian (Infineon Technologies - France), Vincent Gouin (Infineon Technologies - France), Patrick Girard (LIRMM - France), Christian Landrault (LIRMM - France), Alexandre Ney (LIRMM - France), Serge Pravossoudovitch (LIRMM - France), Arnaud Virazel (LIRMM - France)

- 65s) Using FPGA Configuration Memory to Accelerate Yield Learning for Advanced Process,
Jenny Fan (Xilinx Inc. - USA), Xiao-Yu Li (Xilinx Inc. - USA), Ismed Hartanto (Xilinx Inc. - USA)

Session 11 C-Special Session on Analog Production Test #2
Session Chair: J. Rivoir (Verigy, Germany) 
(15:20 ~ 16:20)

- APT2.1) Bluetooth Hopping BER Testing Methodologies on a Production Test Platform,
David Bement (Broadcom Corporation - USA), David Karr (Broadcom Corporation - USA)

- APT2.2) Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC,
Deng Yue (Verigy Shanghai Application Development Center - China)

- APT2.3) Top 5 Issues in Practical Testing of High-Speed Interface Devices,
Takahiro J. Yamaguchi (Advantest Laboratories Ltd.- Japan)





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