IEEE Twelfth Workshop on RTL and High Level Testing 2011

MNIT Jaipur, India November 25-26, 2011

The purpose of this workshop is to bring researchers and practitioners on VLSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. The twelfth workshop on RTL and high level testing (WRTLT'11) will be held in conjunction with the 20th Asian Test Symposium (ATS'11). The workshop aims to encourage the presentation and discussion of truly innovative and “out-of-the-box” ideas aimed at addressing these challenges of high level test. We hope the workshop will provide an ideal forum for future complex system test at higher level of abstraction.

Representative topics include, but not limited to:

· Functional fault modeling

· Microprocessor testing

· Relationship between RTL and gate-level testing

· High level test bench generation

· High level approaches for testing

· RTL ATPG

· RTL BIST

· Design Verification

· SoC/NoC Testing

· Secure Testing

· 3D IC Test

Submission Details:

To present at the Workshop, authors are invited to submit previously unpublished technical proposals. The proposals must be full papers of maximum 8 pages or an extended summary. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords.  Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your proposal by PDF, via easy chair or via

E-mail to : [email protected]

 

Important Dates:

Paper Submission:                      August 31, 2011 (Extended)

Author Notification:                      September 25, 2011

Final Paper Submission:             October 15, 2011

 

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Organizing Committee

 

General Co-Chairs

Rubin Parekhji (TI, IN)

   <parekhji at ti dot com>

MS Gaur (MNIT, IN)

   <gaurms at gmail dot com>

 

Program Co-Chairs

Michiko Inoue (NAIST, JP)

   <kounoe at is dot naist dot jp>

Virendra Singh (IISc, IN)

   <viren at serc dot iisc dot ernet dot in>

 

Finance Chair

Vijay Laxmi (MNIT, IN)

   <vlgaur at gmail dot com>

 

Publication Chair

Susanta Chakravarty (BESU, IN)

   <susanta dot chak at gmail dot com>

 

Publicity Chair

Chia Yee Ooi (UTM, MY)

   <ooichiayee at fke dot utm dot my>

Zhiqiang You (Hunan U., CN)

   <zq_you at 163 dot com>

 

Local Organization Chair

Lava Bhargava (MNIT, IN)

   <lavab at yahoo dot com>

 

Registration Chair

Jaynarayan Tudu (IISc, IN)

   <jaynarayan004 at gmail dot com>

Ashok Sihag (GBU, IN)

 

Web Site Chair

Pawan Kumar (IISc, IN)

   <pawan at rishi dot serc dot iisc dot in>

 

--------------------------------------------------------------

Program Committee

 

Chia Yee Ooi (UTM, MY)

   <ooichiayee at fke dot utm dot my>

 

Anzhela Matrosova (TSU, RU)

   <mau11 at yandex dot ru>

 

Tomokazu Yoneda (NAIST, JP)

   <yoneda at is dot naist dot jp>

 

Huawei Li (CAS, CN)

< lihuawei at ict dot ac dot cn>

 

Seiji Kajihara (KIT, JP)

   kajihara at cse dot kyutech dot ac dot jp

 

Kazumi Hatayama (NAIST, JP)

   <k-hatayama at is dot naist dot jp>

 

Ilia Polian (U.Passau, DE)

   <ilia.polian at uni-passau dot de>

 

Erik Larsson (Linkoeping Univ., SE)

   <erik dot larsson at liu dot se>

 

Masaki Hashizume (Univ. of Tokushima, JP)

   <tume at ee dot tokushima-u dot ac dot jp>

 

Tomoo Inoue (Hiroshima Univ., JP)

   <tomoo at hiroshima-cu dot ac dot jp>

Yasuo Sato (KIT, JP)

   sato at cse dot kyutech dot ac dot jp

 

Satoshi Ohtake (Oita U., JP)

   <ohtake at is dot naist dot jp>

 

Hideyuki Ichihara (HCU, JP)

   <ichihara at hiroshima-cu dot ac dot jp>

 

Xioqiang Wen (KIT, JP)

   wen at cse dot kyutech dot ac dot jp

 

Dong Xiang (Tsinghua Univ., CN)

   <dxiang at tsinghua dot edu dot cn>