[http://www.ip.elec.mie-u.ac.jp/~wrtlt02/]
_____________________________________________________________________
C A L L F O R P A P E R S
WRTLT'02
3rd Workshop on RTL and High Level Testing
November 21-22, 2002
Hyatt Regency Guam, Guam, USA
Held in conjunction with the 11th Asian Test Symposium (ATS'02)
Sponsored by
IEEE Computer Society Test Technology Technical Council
In Corporation with
Technical Group on Dependable Computing, IEICE
_____________________________________________________________________
The purpose of this workshop is to bring researchers and practitioners
on LSI testing from all over the world together to exchange ideas and
experiences on register transfer level (RTL) and high level testing.
WRTLT'02, the third workshop, will be held in conjunction with the 11th
Asian Test Symposium (ATS'02) in tropical island Guam. We hope and
expect this workshop provides an ideal forum for frank discussion on
this important topic for coming age of system-on-a-chip (SoC) devices.
Areas of interest include but are not limited to:
Functional fault modeling
RTL ATPG and fault simulation
RTL DFT
RTL BIST
RTL test for design validation
RTL low power test
Relationship between RTL and gate level testing
High level approaches for testing
SoC Testing
Authors are invited to submit paper proposals for presentation at the
workshop. The proposal may be an extended summary (1,000 words) or a
full paper and should include: title, full name and affiliation of all
authors, 50 words abstract, keywords and the name of contact author.
All submissions should be sent to the following address as Postscript
or PDF attachment.
wrtlt02(at)crl.hitachi.co.jp
*IMPORTANT DATES*
Submission deadline : July 31, 2002
Acceptance notification : August 31, 2002
Final version deadline : to be announced
Photocopies of accepted papers will be handed out to the
attendees at the workshop site.
For up-to-date information on WRTLT'02, visit the workshop website
http://www.ip.elec.mie-u.ac.jp/~wrtlt02/
or contact the workshop chairs.
Guam is so-called America's paradise in the Pacific. There are many
sightseeing spots, such as Lover's Point, Plaza de Espana and Fort
Apugan. For more information on tourism, some links can be found at
the above website.
_____________________________________________________________________
General Chair:
Terumine Hayashi, Mie University, Japan
Program Chair:
Kazumi Hatayama, Hitachi, Ltd., Japan
Finance Chair:
Tsuyoshi Shinogi, Mie University, Japan
Local Arrangements Chair:
Yukiya Miura, Tokyo Metropolitan University, Japan
Registration Chair:
Tomoo Inoue, Hiroshima City University, Japan
Publicity Chair:
Hiroshi Yokoyama, Akita University, Japan
Program Committee
Jianhua Gao, China Kewal K. Saluja, USA
Sandeep K. Gupta, USA Yihe Sun, China
Masaki Hashizume, Japan J. Paulo Teixeira, Portugal
Toshinori Hosokawa, Japan Xiaoqing Wen, USA
Michiko Inoue, Japan Cheng-Wen Wu, Taiwan
Kazuhiko Iwasaki, Japan Shiyi Xu, China
Xiaowei Li, China Hee Yong Youn, Korea
Zhongcheng Li, China Dafang Zhang, China
WRTLT Steering Committee
Chair:
Yinghua Min, China
Members:
Hideo Fujiwara, Japan Kewal K. Saluja, USA
Terumine Hayashi, Japan Hideo Tamamoto, Japan
Kazuhiko Iwasaki, Japan J. Paulo Teixeira, Portugal
Xiaowei Li, China Dafang Zhang, China
Alex Orailoglu, USA
_____________________________________________________________________
WRTLT'02 Advance Program
Technical sessions are held at San Vitores & Magellan.
Wednesday, November 20
18:30-20:00 Welcome Reception
Thursday, November 21
8:30- 9:30 Opening Remarks and Invited Talk
General Chair's Message
T. Hayashi - Mie University
PC Chair's Message
K. Hatayama - Hitachi Ltd.
Invited Talk - Native-Mode Built-In Self-Test
J.A.Abraham - U. of Texas at Austin, USA
9:30-10:00 Coffee Break
10:00-11:40 Session 1: SoC Test
S1-1 Optimal Test Access Mechanism Scheduling using Preemption
and Reconfigurable Wrappers
E. Larsson, H. Fujiwara - NAIST, Japan
S1-2 Optimal Bandwidth Allocation in Concurrent SoC Test Under
Pin Number Constraints
I. Polian, B. Becker - Albert-Ludwigs U., Germany
S1-3 Design for Consecutive Transparency of RTL circuits
T. Yoneda, H. Fujiwara - NAIST, Japan
S1-4 Effective Test Program Induction for Microprocessor IP
Core
F. Corno, F. Cumani, M. Sonza Reorda, G. Squillero -
Poli. de Torino, Italy
11:40-13:10 Lunch Time
13:10-14:50 Session 2: RTL DFT and BIST
S2-1 A Non-scan DFT Method for RTL Data Path Circuits with
Various Bit Width
H. Date, T. Hosokawa, M. Miyazaki and M. Muraoka -
STARC, Japan
S2-2 A Partial Scan Design with Orthogonal Scan Paths
T. Inoue - Hiroshima City U., Japan, H. Fujiwara -
NAIST, Japan
S2-3 Hierarchical BIST: Test-Per-Clock BIST with Low Overhead
K. Yamaguchi, M. Inoue, H. Fujiwara - NAIST, Japan
S2-4 Application of Partially Rotational Scan Technique to
Processor Circuits
K. Ichino, K. Watanabe, M. Arai, S. Fukumoto,
K. Iwasaki - Tokyo Metropolitan U.
14:50-15:20 Coffee Break
15:20-17:00 Session 3: Test and Synthesis
S3-1 Test Vector Overlapping for Test Cost Reduction in Core
Testing
T. Shinogi, Y. Yamada, T. Yoshikawa, S. Tsuruoka,
T. Hayashi - Mie U., Japan
S3-2 Defect Based Functional Test for Non-Volatile Memory
Disturb Faults
M. Mohammad, K. K. Saluja - U. of Wisconsin, USA
S3-3 Monitoring for the Real Time Constraints
C. Peng, B. Wu, X. Sun, Z. Chen - Fudan U., China
S3-4 Simplification of Incomplete Specified Machine Based on
Genetic Algorithm Implementing Dormant Mechanism
M. Hashizume, T. Matsushima, T. Shimamoto,
H. Yotsuyanagi, T. Tamesada - U. of Tokushima, Japan,
A. Sakamoto - Kochi U., Japan
18:30-20:30 Banquet
Friday, November 22
8:30-10:10 Session 4: ATPG and Fault Simulation
S4-1 A Novel Approach to RTL Behavioral Implication
Z. Yin, H. Li, and X. Li - ICT/CAS, China
S4-2 Efficient Hierarchical Test Generation for RTL Circuits
Y.-J. Xue, H. Wang, S.-Y. Yang, J.-H. Xing, Y.-C. Deng
- Tsinghua U., China
S4-3 X-Maximal Test Set Generation for Combinational Circuits
T. Hayashi, Y. Morimoto, T. Shinogi, H. Kita, H. Takase
- Mie U., Japan
S4-4 Using Verilog VPI for Serial Fault Simulation in a Test
Generation Environment
P. A. Riahi, Z. Navabi, F. Karimi, F. Lombardi -
Northeastern U., USA
10:10-10:40 Coffee Break
10:40-11:55 Session 5: Effectiveness in Test
S5-1 A Test Plan Grouping Method to Reduce Test Length and
Test Controllers for RTL Data Paths
T. Hosokawa, H. Date, M. Miyazaki, M. Muraoka - STARC,
Japan
S5-2 Test Data Volume Reduction Using Statistical Encoding
for Multiple Scan Chain Designs
K. Taniguchi, K. Miyase, S. Kajihara - Kyushu Inst.
of Tech., Japan, I. Pomeranz - Purdue U., USA,
S. M. Reddy - U. of Iowa, USA
S5-3 On Effective Criterion of Path Selection for Delay Testing
M. Fukunaga, S. Kajihara - Kyushu Inst. of Tech., Japan,
S. Takeoka, S. Yoshimura - Matsushita Elec., Japan
11:55-12:00 Closing Remark