9th Asian Test Symposium, ATS'00

The Ninth Asian Test Symposium (ATS2000)

December 4-6, 2000
Grand Hotel, Taipei, Taiwan

(Sponsored by IEEE Computer Cociety, TTTC and National Cheng Kung


The ATS2000 will follow the tradition established by its predecessors
and continue to explore current concepts and future trends in electronic testing.
In addition, "Cooperation and Integration" has been selected as the theme of the
symposium. Thus, papers on cooperative efforts between design and test teams
as well as between academia and industry are highly solicited.


Original contributions related to electronis circuit & system testing are
sought. Topics of interest include, but not limited to, the following:

(A) Test generation & fault simulation (B) Failure analysis & fault modeling
(C) Design for testablility (D)Built-in self-test
(E) Fault diagnosis (F) Fault tolerance &
error correction
(G)Analog & mixed signal testing (H) Functional testing
(I) Memory testing (J) IDDQ testing
(K) Wafer-level testing (L)Test economics
(M) System-on-chip testing (N)P1500 & boundary scan
(O) Integration of design and test (P) Test experience in industry
(Q) Software testing (R) Automatic test equipment


Electronic submissions (postcript or PDF files) are preferred.
Detailed instructions can be found on the World Wide Web at
URL: http://ats2000.ee.ncku.edu.tw. In case of hardship one may request
special instruction by sending email to [email protected].
Basically a submission should contain a full paper of no more than 4000 words
including an abstract of 50-200 words, and a seperate cover page containing or
1) the title of the paper,
2) the affiliation and address of each
3) the contact author (including the post and e-mail addresses)
4) the categories that the paper belongs to (using the letter(s) given above or create one
if necessary).
The submissions will be considered evidence that upon
acceptance the author(s) will prepare the final manuscript in time for inclusion in
the proceeding and will present the paper at the Symposium. ATS2000 will
present a best paper award based on the evaluations of reviewers, attendees, and
an invited panel of judges.

Important Dates:

Deadline for Submission: April 15, 2000
Notification of Acceptance: July 15, 2000
Deadline for Final Maunsucript: September 15, 2000

About Taiwan and Taipei

Taiwan is currently one of the world's major computer hardware and
IC chip producing country. Taipei is the capital city and has long been the
political, financial, economic and cultural center of Taiwan. With its harmonic
mixing of Oriental traditions and Western cultures, plus its hospitable people
and fast-growing economics, Taipei has developed itself into a unique
international metropolis.

The average temperature in December in Taipei is around 18 C (64 F).

General Chair: Professor Cheng-Wen Wu, National Tsing Hwa University
Program Cochairs: Professor Kuen-Jong Lee, National Cheng Kung University
Professor Chau-Chin Su, Naitonal Central University

Program Committee:

V.D. Arrawal, R. Aitken, M.A. Breuer, S. Chakravarty,
T.-Y Chang, J.E. Chen, K.T. Cheng, W.T. Cheng, B. Cockburn, S.
Demidenko, J. Figueras, H. Fujiwara, H. Hiraishi, A. Ivanov,
W.B. Jone, J.Y. Jou, S. Kajihara, B. Kaminska K. Kinoshita A.
Kundu, C.L. Lee, B.D. Liu, Y. Malaiya, E.J. McCluskey Y.H.
Min, M. Nicolaidis, I. Pomeranz, P. Prinetto, J. Rajski, C.P. Ravikumar,
A.M. Reddy K. Saluja J. Savir S. C. Seth
T. Shinogi, S. Soma, H. Takahashi A.J. van de Goor S.J. Wang X. Wen
C.L. Wey M.W.T. Wong S. Xu T.W. Williams S.Yano
T. Yamada M.Yoshida Y. Zorian

Further Information:

Email: [email protected]

Advance Program
Asian Test Symposium 2000 (ATS2000)

Grand Hotel, Taipei, Taiwan
December 4-6, 2000
For registration & hotel reservation, use the forms in the attached
Word files reg.doc and hotel.doc, or download the forms from
For any question, please send email to: [email protected]


Tutorial 1: High Performance/Delay Testing
Monday, Dec. 4, 8:30am-12:00pm and 1:30pm-5:00pm; R110
Presenter: Sudhakar M. Reddy, University of Iowa, USA
Chair: Shi-Yu Huang, National Tsing Hua University, Taiwan

Tutorial 2: SoC Testing & P1500 Standard
Monday, Dec. 4, 8:30am-12:00pm and 1:30pm-5:00pm; R105
Presenter: Yervant Zorian, LogicVision, USA
Chair: Tsin-Yuan Chang, National Tsing Hua University, Taiwan

Exhibits: Dec. 5-6, 8:30am-6:00pm.
Room number and company names will be announced in November on
the ATS2000 web site: http://www.ats2000.ee.ncku.edu.tw/

Opening Ceremony: Tuesday, Dec. 5, 8:10 am - 8:30 am; R100
Cheng-Wen Wu, General Chair
Kuen-Jong Lee & Chau-Chin Su, Program Cochairs.

Keynote Speech I: Testing in the Fourth Dimension
Tuesday, Dec. 5, 8:30 am - 9:20 am; R100
Presenter: Vishwani D. Agrawal, Bell Labs., USA
Chair: Kwang Ting (Tim) Cheng, UCSB, USA

Keynote Speech II: Challenges For The Academic Test Community
Tuesday, Dec. 5, 9:20 am - 10:10 am; R100
Presenter: Melvin A. Breuer, USC, USA
Chair: Kwang Ting (Tim) Cheng, UCSB, USA

Industry Sessions

Industry Session I: CAD Tools on Testing
Tuesday, Dec. 5, 10:30 am - 12:00pm; R100
Session Chair: Jing-Yang Jou, NCTU, Taiwan

10:30-10:45 DFT and BIST Techniques for the Future
Hsin-Po Wang, SynTest Inc., Taiwan and
Jon Turino, SynTest Inc., US

10:45-11:00 DFT Closure
F. Hayat, T.W. Williams, R. Kapur and
D. Hsu, Synnpsys Inc., US

11:00-11:15 Current Status and Future Trend on CAD Tools for
VLSI Testing
Wu-Tung Cheng, Mentor Graphics Corporation, USA

11:15-11:30 Yervant Zorian

11:30-12:00 Discussion

Industry Session II: Taiwan Test Industry: Value Added Testing in the New Millennium
Tuesday, Dec. 5, 1:30 pm - 2:50 pm; R100
Session Chair: Chung-Len Lee, NCTU, Taiwan

Panel Discussions

Panel I: Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way?
Tuesday, Dec. 5, 3:10 pm - 4:35 pm; R110
Moderator: Chin-Long Wey, Michigan State University, USA
Jose Luis Huertas, Instituo Microelectronica de Sevilla-CNM, SPAIN
Yeon-Chen Nieu, Teradyne, Taiwan
Adam Osseiran, Fluence Technology Inc. (Europe), Switzerland

Panel II: Collaboration between Industry and Academia in Test Research
Tuesday, Dec. 5, 3:10 pm - 4:35 pm; R105
Moderator: Kwang-Ting (Tim) Cheng, UCSB, USA
Vishwani Agrawal, Bell Labs, USA
Jing-Yang Jou, NCTU, Taiwan
Li-C. Wang, Motorola/UCSB, USA
Chi-Feng Wu, Philips, Taiwan
Shianling Wu, Lucent, USA

Fringe Meeting (open to public)

Topic: SoC Testing & P1500 Standard
Wednesday, Dec. 6, 8:00 am - 9:35 am; R105
Chair: Shianling Wu, Lucent, USA
Co-chair: Yervan Zorian, LogicVision, USA
Xinghao Chen, IBM, USA
Martin Fischer, Agilent, Germany
Douglas Kay, Cisco, USA
J.C. Frank Lien, Actel, USA
Rubin A. Parekhji, TI, India
Phil Smith, Teradyne, USA
L.T. Wang, SynTest, Taiwan
Technical Paper Sessions

Session A1: Analog & Mixed Signal Test I
Tuesday, Dec. 5, 4:45 pm - 6:00 pm; R110
Chair: Kiyoshi Furuya, Chuo University, Japan

A1-1 Test Generation for Fault Isolation in Analog Circuits Using Behavioral Models
S. Cherubal and A. Chatterjee
A1-2 Fault Diagnosis for Linear Analog Circuits
J.-W. Lin, C.-L. Lee, C.-C . Su, and J.-E. Chen
A1-3 Testing Mixed-Signal Cores: Practical Oscillation-Based Test in an Analog Macrocell
G. Huertas, D. Vazquez, E. Peralias, A. Rueda, and J. Huertas
A1-4 New Built-In Self-Test Technique Based on Addition/Subtraction of Selected Node Voltages
K. Ko and M. Wong

Session A2: Memory Built-In Self-Test and Self-Diagnosis
Tuesday, Dec. 5, 4:45 pm - 6:00 pm; R105
Chair: Ad J. van de Goor, Delft University of Technology, The Netherlands

A2-1 A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM
C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin
A2-2 An FPGA-Based Re-Configurable Functional Tester for Memory Chips
J.-R. Huang, C. Ong, K. Cheng, and C. Wu
A2-3 BIST TPG for SRAM Cluster Interconnect Testing at Board Level
C.-H. Chiang and S. Gupta
A2-4 Efficient Built-In Self-Test Algorithm for Memory
S.-J. Wang and C.-J. Wei

Session B1: Analog & Mixed Signal Test II
Wednesday, Dec. 6, 8:00 am - 9:35 am; R110
Chair: M.D. Shieh, National Yunlin Technical University, Taiwan

B1-1 Optimal Test-Set Generation for Parametric Fault Detection in Switched Capacitor Filters
W. Choi, R. Harjani, and B. Vinnakota
B1-2 TI-BIST: A Temperature Independent Analog BIST for Switched-Capacitor Filters
L. Carro, E. Cota, M. Lubaszewski, Y. Bertrand, F. Azais, and M. Renovell
B1-3 Analog Circuit Equivalent Faults in the D.C. Domain
M. Worsman, M. Wong, and Y. Lee
B1-4 A Methodology for Fault Model Development for Hierarchical Linear Systems
Y.-C. Huang, C.-L. Lee, J.-W. Lin, J.-E. Chen, and C.-C. Su
B1-5 Testing a PWM Circuit Using Functional Fault Models and Compact Test Vectors for Operational Amplifiers
J. Calvano, V. Alves, and M. Lubaszewski

Session B2: Fault Simulation & Timing Simulation
Wednesday, Dec. 6, 8:00 am - 9:35 am; R102
Chair: Kazumi Hatayama, Hitachi, Japan

B2-1 A New Framework for Static Timing Analysis, Incremental Timing Refinement, and Timing Simulation
L.-C. Chen, S. Gupta, and M. Breuer
B2-2 On the Feasibility of Fault Simulation Using Partial Circuit Descriptions
I. Pomeranz and S. Reddy
B2-3 Fsimac: A Fault Simulator for Asynchronous Sequential Circuits
S. Sur-Kolay, M. Roncken, K. Stevens, P. Chaudhuri, and R. Roy
B2-4 Simulation of Resistive Bridging Fault to Minimize the Presence of Intermediate Voltage and Oscillation in CMOS Circuits
A. Keshk, Y. Miura, and K. Kinoshita
B2-5 Non-Invasive Timing Analysis of IBM G6 Microprocessor L1 Cache Using Picosecond Imaging Circuit Analysis
S. Polonsky, M. Mc Manus, D. Knebel, S. Steen, and P. Sanda

Session C1: Fault Analysis I
Wednesday, Dec. 6, 9:55 am - 11:10 am; R110
Chair: Shiyi Xu, Shanghai University of Science and Technology, China

C1-1 An Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests
S. Hamdioui and Ad J. van de Goor
C1-2 Enhanced Untestable Path Analysis Using Edge Graphs
S. Kajihara, T. Shimono, I. Pomeranz, and S. Reddy
C1-3 A Waveform Simulator Based on Boolean Process
L. Li, X. Yu, C.-W. Wu, and Y. Min
C1-4 On the Superiority of DO-RE-ME / MPG-D over Stuck-at-Based Defective Part Level Prediction
J. Dworak, M. Grimaila, B. Cobb, T-C. Wang, Li-C. Wang, and M. Mercer

Session C2: Test Generation I
Wednesday, Dec. 6, 9:55 am - 11:10 am; R102
Chair: Yukihiro Iguchi, Meiji University, Japan

C2-1 Compaction-Based Test Generation Using State and Fault Information
A. Giani, S. Sheng, M. Hsiao, and V. Agrawal
C2-2 Test Sequence Compaction for Sequential Circuits with Reset States
Y. Higami, Y. Takamatsu, and K. Kinoshita
C2-3 SPIRIT: Satisfiability Problem Implementation for Redundancy Identification and Test Generation
E. Gizdarski and H. Fujiwara
C2-4 Forecasting the Efficiency of Test Generation Algorithms for Digital Circuits
S. Xu and W. Cen

Session C3: Functional Testing
Wednesday, Dec. 6, 9:55 am - 11:10 am; R105
Chair: Tomoo Inoue, Hiroshima University, Japan

C3-1 Fast Hierarchical Test Path Construction for DFT-Free Controller-Datapath Circuits
Y. Makris, J. Collins, and A. Orailo?lu
C3-2 Faster Processing for Microprocessor Functional ATPG
J. Hirase and S. Yoshimura
C3-3 Verification of Deadlock Free Property of High Level Robot Control
H. Hiraishi
C3-4 Functional Testing of Microprocessors with Graded Fault Coverage
R. Kannah and C. Ravikumar

Session D1: Built-In Self-Test I
Wednesday, Dec. 6, 11:20 am - 12:20 pm; R110
Chair: Jacob Savir, New Jersey Institute of Technology

D1-1 Single-Control Testability of RTL Data Paths for BIST
T. Masuzawa, M. Izutsu, H. Wada, and H. Fujiwara
D1-2 A BIST Methodology for At-Speed Testing of Data Communications Transceivers
S. Lin, S. Mourad, and S. Krishnan
D1-3 High-Speed Generation of LFSR Signatures
M.-D. Shieh, H.-F. Lo, and M.-H. Sheu

Session D2: Software Testing & Test Synthesis
Wednesday, Dec. 6, 11:20 am - 12:20 pm; R102
Chair: Wen-Ben Jone, National Chung Cheng University, Taiwan

D2-1 Strong Self-Testability for Data Paths High-Level Synthesis
X. Li, T. Masuzawa, and H. Fujiwara
D2-2 Generating Test Items for Checking Illegal Behaviors in Software Testing
M. Hirayama, J. Okayasu, T. Yamamoto, O. Mizuno, and T. Kikuno
D2-3 Using Genetic Algorithms for Test Case Generation in Path Testing
J.-C. Lin and P.-L. Yeh

Session D3: Embedded-Core Testing
Wednesday, Dec. 6, 11:20 am - 12:20 pm; R105
Chair: Douglas Kay, Cisco, USA

D3-1 A Hierarchical Test Control Architecture for Core Based Design
K.-J. Lee and C.-I. Huang
D3-2 Embedded Core Testing Using Genetic Algorithms
R. Xu and M. Hsiao
D3-3 Functional Testing and Fault Analysis Based Fault Coverage Enhancement Techniques for Embedded Core Based Systems
A. Bagwe and R. Parekhji

Session E1: Memory Testing
Wednesday, Dec. 6, 1:30 pm - 3:05 pm; R110
Chair: Rubin A. Parekhji, TI, India

E1-1 Detection of SRAM Cell Stability by Lowering Array Supply Voltage
D.-M. Kwai, H.-W. Chang, H.-J. Liao, C.-H. Chiao, and Y.-F. Chou
E1-2 A Realistic Fault Model for Flash Memories
Y.-L. Horng, J.-R. Huang, and T.-Y. Chang
E1-3 Impact of Memory Cell Array Bridges on the Faulty Behavior in Embedded DRAMs
Z. Al-Ars and Ad J. van de Goor
E1-4 Memory Test Time Reduction by Interconnecting Test Items
W.-J. Wu and C. Tang
E1-5 An Efficient Parallel Transparent Diagnostic BIST
D. Huang and W. Jone

Session E2: Test Generation II
Wednesday, Dec. 6, 1:30 pm - 3:05 pm; R102
Chair: Christian Landrault, LIRMM, France

E2-1 Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
W.-Y. Chen, S. Gupta, and M. Breuer
E2-2 Testing Programmable Interconnect Systems: An Algorithmic Approach
B. Liu, F. Lombardi, and W. Huang
E2-3 Reducing Test Application Time for Full Scan Circuits by the Addition of Transfer Sequences
I. Pomeranz and S. Reddy
E2-4 TOF: A Tool for Test Pattern Generation Optimization of an FPGA Application-Oriented Test
M. Renovell, J. Portal, P. Faure, J. Figueras, and Y. Zorian
E2-5 Formal Verification of Data-Path Circuits Based on Symbolic Simulation
Y. Morihiro and T. Yoneda

Session E3:IDDQ Testing
Wednesday, Dec. 6, 1:30 pm - 3:05 pm; R105
Chair: Sying-Jyan Wang, National Chung Hsing University, Taiwan

E3-1 Is IDDQ Testing not Applicable for Deep Submicron VLSI in Year 2011?
C.-W. Lu, C.-L. Lee, C. Su, and J.-E. Chen
E3-2 High Speed IDDQ Test and Its Testability for Process Variation
M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, and M. Takeda
E3-3 Memory Reduction of IDDQ Test Compaction for Internal and External Bridging Faults
T. Maeda and K. Kinoshita
E3-4 A High-Speed IDDQ Sensor Implementation
Y. Antonioli, T. Inufushi, S. Nishikawa, and K. Kinoshita
E3-5 Cyclic Greedy Generation Method for Limited Number of IDDQ Tests
T. Shinogi, M. Ushio, and T. Hayashi

Session F1: Built-In Self-Test II
Wednesday, Dec. 6, 3:25 pm - 4:40 pm; R110
Chair: Shianling Wu, Lucent, USA

F1-1 Accelerated Test Pattern Generators for Mixed-Mode BIST Environments
W.-L. Wang and K.-J. Lee
F1-2 Effective Parallel Processing Techniques for the Generation of Test Data for a Logic Built-In Self-Test System
P. Chang, B. Keller, and S. Paliwal
F1-3 Design and Testing of Fast and Cost Effective Serial Seeding TPGs Based on One-Dimensional Linear Hybrid Cellular Automata
A. Hlawiczka and M. Kopec
F1-4 An Efficient BIST Design Using LFSR-ROM Architecture
L. Li and Y. Min

Session F2: Testability Analysis and Design for Testability
Wednesday, Dec. 6, 3:25 pm - 4:25 pm; R102
Chair: Xinghao Chen, IBM, USA

F2-1 Novel Techniques for Improving Testability Analysis
Y.-H. Su, C.-H. Cheng, and S.-C. Chang
F2-2 A Class of Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
M. Inoue, E. Gizdarski, and H. Fujiwara
F2-3 Design for Sequential Testability: An Internal State Reseeding Approach for 100% Fault Coverage
M. Flottes, C. Landrault, and A. Petitqueux

Session F3: Fault Tolerance
Wednesday, Dec. 6, 3:25 pm - 4:40 pm; R105
Chair: J.C. Frank Lien, Actel, USA

F3-1 Testing Approach within FPGA-Based Fault Tolerant Systems
A. Doumar and H. Ito
F3-2 Transient-Fault Tolerant VHDL Descriptions: A Case Study for Area Overhead Analysis
F. Vargas and A. Amory
F3-3 Fault Tolerant Multistage Interconnection Networks with Widely Dispersed Paths
N. Kamiura, T. Kodera, and N. Matsui
F3-4 A Testable/Fault-Tolerant FFT Processor Design
S.-K. Lu, J.-S. Shih, and C.-W. Wu

Session G1: Fault Analysis II
Wednesday, Dec. 6, 4:50 pm - 5:50 pm; R110
Chair: Mike Wong, Hong Kong Polytechnic University, Hong Kong

G1-1 Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits
C.-H. Cheng, W.-B. Jone, J.-S. Wang, and S.-C. Chang
G1-2 Testing Domino Circuits in SOI Technology
E. MacDonald and N. Touba
G1-3 A Case Study of Failure Analysis and Guardband Determination for a 64M-Bit DRAM
C.-T. Kao, S. Wu, and J. Chen

Session G2: Low-Power Testing
Wednesday, Dec. 6, 4:50 pm - 5:50 pm; R102
Chair: C.P. Ravikumar, Indian Institute of Technology, India

G2-1 Peak-Power Reduction for Multiple-Scan Circuits during Test Application
K.-J. Lee, T.-C. Huang, and J.-J. Chen
G2-2 An Adjacency-Based Test Pattern Generator for Low Power BIST Design
P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch
G2-3 Distribution-Graph Based Approach and Tree Growing Technique in Power-Constrained Block-Test Scheduling
V. Muresan, X. Wang, V. Muresan, and M. Vladutiu

Session G3: Self-Checking Circuits and Concurrent Fault Detection
Wednesday, Dec. 6, 4:50 pm - 5:45 pm; R105
Chair: Yinghua Min, Academia Sinica, China

G3-1 A Method for Determining Whether Asynchronous Circuits Are Self-Checking
M. Liebelt and C.-C. Lim
G3-2 On Testing Safety-Sensitive Digital Systems
J. Savir
G3-3 Accumulation-Based Concurrent Fault Detection for Linear Digital State Variable Systems
I. Bayraktaroglu and A. Orailoglu

Registration form and Hotel Reservation Form

Both forms can be downloaded from http: //www.ats2000.ee.ncku.edu.tw/
or use the attached files reg.doc and hotel.doc.


There are three ways to reach the Grand Hotel from CKS International
Airport: by taxi, by public bus, and by the Grand Hotel shuttle bus.
The most convenient way is to reserve the Grand Hotel shuttle bus using
the hotel reservation form. Alternatively, you can either take a taxi from
the CKS airport to the Grand Hotel directly, or take any public bus to
Taipei City and then take a taxi to the Grand Hotel. The taxi fare to the
Grand Hotel is roughly $NT1,500 (US$50).

Organizing Committee

General Chair:
Cheng-Wen Wu, National Tsing Hua University, Taiwan

Program Co-Chairs:
Kuen-Jong Lee, National Cheng-Kung University, Taiwan
Chau-Chin Su, National Central University, Chung-Li, Taiwan

Local Arrangement Chair: Shyh-Jye Jou, National Central University, Taiwan
Finance Cochairs:
Bin-Da Liu, National Cheng Kung University, Taiwan
Jyuo-Min Shyh, Industrial Technology Research Institute, Taiwan
Publication Cochairs:
Wen-Ben Jone, National Chung-Cheng University, Taiwan
Tai-Haur Kou, National Cheng Kung University, Taiwan
Registration Chair: Jwu-E Chen, Chung-Hua University, Taiwan
Exhibit Chair: Jing-Yang Jou, National Chiao-Tung University, Taiwan
Tutorial Chair: Tsin-Yuan Chang, National Tsing-Hua University, Taiwan
Publicity Chair: Chung-Len Lee, National Chiao-Tung University, Taiwan
Secretariat: Jing-Jou Tang, Southern Taiwan University of Technology, Taiwan
USA Liaison: K. T. Tim Cheng UCSB, USA
European Liaison: Michael Nicolaidis, TIMA, France

Program Committee

Vishwani D. Agrawal
Rob Aitken
Melvin A Breuer
Sreejit Chakravarty
Tsin-Yuan Chang
Jwu-E Chen
Kwang-Ting (Tim) Cheng
Wu-Tung Cheng
Bruce Cockburn
Serge Demidenko
Joan Figueras
Hideo Fujiwara
Hiromi Hiraishi
Andre Ivanov
Wen-Ben Jone
Jing-Yang Jou
Seiji Kajihara
Bozena Kaminska
Kozo Kinoshita
Sandip Kundu
Chung-Len Lee
Bin-Da Liu
Yashwant Malaiya
Edward J. McCluskey
Yinghua Min
Michael Nicolaidis
Irith Pomeranz
Paolo Prinetto
Janusz Rajski
C.P. Ravikumar
Sudhakar M. Reddy
Kewal K. Saluja
Jacob Savir
Sharad C. Seth
Tsuyoshi Shinogi
Mani Soma
Hiroshi Takahashi
Ad J. Van de Goor
Sying-Jyan Wang
Xiaoqing Wen
Ching-Long Wey
Tom W. Williams
Mike W. T. Wong
Shiyi Xu
Teruhiko Yamada
Seiken Yano
Massaki Yoshida
Yervant Zorian