5th Asian Test Symposium, ATS'96

                    CALL FOR PAPERS
The Fifth Asian Test Symposium (ATS'96)
November 20-22, 1996
National Tsing Hua University
Hsinchu, Taiwan


Professor Chung-Len Lee
Department of Electronic Engineering
National Chiao Tung University
Hsinchu, Taiwan


Professor Cheng-Wen Wu
Department of Electrical Engineering
National Tsing Hua University
Hsinchu, Taiwan


Local Arrangements Chair: Youn-Long Lin (NTHU)
Finance Chair: Ting-Ting Hwang (NTHU)
Publications Chair: Wen-Zen Shen (NCTU)
Registration Cochairs: Chung-Hao Wu (NTHU) & Jing-Yang Jou (NCTU)
Tutorials Chair: Tsin-Yuan Chang (NTHU)
Exhibits Chair: Jyuo-Min Shyu (ITRI)
Publicity Cochairs: Mely Chen (ITRI) & Jen-Sheng Hwang (CIC, NSC)
US Liaison: Kwang-Ting (Tim) Cheng (UCSB)
Europe Liaison: Bernard Courtois (TIMA)


V.D. Agrawal, M.A. Breuer, P.P.Chaudhuri, J.-E. Chen, M. Chen,
T.H. Chen, K.-T. Cheng, Y.-H. Choi, T.-Y. Chang, H. Fujiwara,
H. Hiraishi, T.-T. Hwang, W.-B. Jone, J.-Y. Jou, K. Kinoshita,
K.-J. Lee, C.-L. Lee, D.H. Lee, C.-S. Lin, M. C.-J. Lin, Y.-L. Lin,
Y.H. Min, E.S. Park, D.K. Pradhan, P. Prinetto, J. Rajski,
S.M. Reddy, R.K. Roy, T. Sasao, W.-Z. Shen, W. Shih, J.-M. Shyu,
C.-C. Su, M. Soma, Y. Takamatsu, A.J. van de Goor, S.-J. Wang,
C.-L. Wey, C.-W. Wu, T.W. Williams, A. Yamada, T. Yamada



Wednesday November 20, 1996

08:30 - 12:00 Tutorial 1 Basic Memory Testing
(Rm. B01) (Prof. Ad J. van de Goor)

08:30 - 12:00 Tutorial 2 Mixed-Signal Fault Models and Design for
Test (I)
(Rm. B02) (Prof. Chin-Long Wey)

13:30 - 17:00 Tutorial 3 Advanced Memory Testing
(Rm. B01) (Prof. Ad J. van de Goor)

13:30 - 17:00 Tutorial 4 Mixed-Signal Fault Models and Design for
Test (II)
(Rm. B02) (Prof. Mani Soma)
18:00 - 20:00 Reception

Thursday November 21, 1996

07:30 Registration

08:00 Opening ceremony

08:20 - 09:20 Keynote Speech
Challenges in Testing
(Prof. Sudhakar M. Reddy)
Chair: Kuen-Jong Lee
09:20 - 09:40 B r e a k

SESSION 1A Test Pattern Generation
Chair: K.-T. (Tim) Cheng
Time: 09:40 - 12:10 Room: B01

1A - 1 Redundancy Identification Using Transitive Closure,
Vishwani D. Agrawal , Michael L. Bushnell, Qing Lin
AT&T Bell Labs., Rm. 2C-476, NJ U.S.A.; Electrical and
Computer Eng. Dept., Rutgers Univ., U.S.A.

1A - 2 Invalid State Identification for Sequential Circuit Test
Generation, Hsing-Chung Liang, Chung Len Lee, Jwu E Chen
Dept. of Electronics Eng., National Chiao Tung Univ.,
Taiwan; Dept. of Electrical Eng., Chung Hwa Polytechnic
Institute, Hsinchu, Taiwan

1A - 3 On Test Generation for Interconnected Finite-State
Machines - The Input Sequence Propagation Problem,
Irith Pomeranz, Sudhakar M. Reddy, Dept. of Electrical
and Computer Eng., Univ. of Iowa, U.S.A.

1A - 4 Hierarchical Test Generation with Built-in Fault Diagnosis,
Dirk Stroobandt, Jan Van Campenhout, Dept. of Electronics
and Info. Systems, Univ. of Ghent, Belgium

1A - 5 Circuit Partitioned Automatic Test Pattern Generation
Constrained by Three-State Buses and Restrictors, J.Th.
van der Linden, M.H. Konijnenburg, A.J. van de Goor,
Delft Univ. of Technology, Faculty of Electrical Eng., The

1A - 6 E-Groups: A New Technique for Fast Backward Propagation
in System Level Test Generation, M. Nicolaidis, R.A.
Parekhji, M. Boudjit Laboratory TIMA/INPG, France


SESSION 1B Board System Level Test
Chair: Bernard Courtois
Time: 09:40 - 12:10 Room: B02

1B - 1 Hybrid Pin Control Using Boundary-Scan And Its Applications,
Wuudiann Ke, Bell Lab., Lucent Technologies, Test and
Reliability Center, Princeton, U.S.A.

1B - 2 Hierarchical Testing Using the IEEE Std 1149.5 Module
Test and Maintenance Slave Interface Module, Jin-Hua Hong,
Chung-Hung Tsai, Cheng-Wen Wu, Dept. of Electrical Eng.,
NTHU, Taiwan

1B - 3 Testing and Diagnosis of Board Interconnect Faults for
Microprocessor-Based Systems, Po-Chin Hsu, Sying-Jyan Wang,
Institute of Computer Science, NCHU, Taiwan

1B - 4 Syndrome Simulators and Syndrome Test for Unscanned
Interconnects, Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou,
Yuan-Tzu Ting, Dept. of Electrical Eng. NCU, Taiwan;
Chung-Shan Institute of Sci. Technology, Lung-Tan, Taiwan

1B - 5 A Test Methodology for Interconnect Structures of LUT-based
FPGAs, Hiroyuki Michinishi,Tokumi Yokohira, Takuji Okamoto,
Tomoo Inoue , Hideo Fujiwara, Dept. of Information Technology,
Faculty of Eng., Okayama Univ.,
Japan; Graduate School of Info. Sci., Nara Institute of Sci.
and Technology, Japan

1B - 6 Testable Design and Testing of MCMs Based on Multifrequency
Scan, Kuochen Wang and Wang-Dauh Tseng, Dept. of Computer
and Info. Sci., National Chiao Tung Univ., Hsinchu, Taiwan

12:10 - 13:25 L u n c h

SESSION 2A Design for Testability
Chair: Hideo Fujiwara
Time: 13:25 - 15:05 Room: B01

2A - 1 A Consistent Scan Design System for Large Scale ASICs
Yoshihiro Konno, Tatsushige Bitoh, Koji Saga, Seiken Yano
CAD Eng. Dept., NEC Corporation, Tokyo, Japan

2A - 2 A Design for Testability Method Using RTL Partitioning,
Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta,
Michiaki Muraoka, Semiconductor Research Center, Matsushita
Electric Industrial Co., Ltd., Osaka, Japan

2A - 3 Partially Parallel Scan Chain for Test Length Reduction by
Using Retiming Technique, Yoshinobu Higami, Seiji Kajihara,
Kozo Kinoshita, Dept. of Applied Physics, Faculty of Eng.,
Osaka Univ., Osaka, Japan; Dept. of Computer Sci. and
Electronics, Kyusyu Institute of Technology, Japan

2A - 4 Combination of Automatic Test Pattern Generation and Built-in
Intermediate Voltage Sensing for Detecting CMOS Bridging
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai
Dept. of Electrical Eng., NCKU, Tainan, Taiwan


SESSION 2B Concurrent Error Detection Fault Tolerance
Chair: Michael Bushnell
Time: 13:25 - 15:05 Room: B02

2B - 1 On Design of Fail-Safe Cellular Arrays, Naotake Kamiura,
Yutaka Hata, Kazuharu Yamato, Dept. of Computer Eng.,
Faculty of Eng., Himeji Institute of Technology, Shosha
Himeji, Japan)

2B - 2 Concurrent Error Detection and Fault Location in a
Fast ATM Switch, Yoon-Hwa Choi, Pong-Gyou Lee, Dept.
of Computer Eng., Hongik Univ., Seoul, Korea

2B - 3 Formal Verification of Self-Testing Properties of
Combinational Circuits, Kazou Kawakubo, Koji Tanaka,
Hiromi Hiraishi, Faculty of Eng., Fukuyama Univ.,
Hiroshima, Japan; Faculty of Eng., Kyoto Sangyo Univ.,
Kyoto, Japan

2B - 4 Constructing an Edge-Route Guaranteed Optimal
Fault-Tolerant Routing for Biconnected Graphs,
Yupin Luo, Shiyuan Yang, Dongchen Hu, Dept. of
Automation, Tsinghua University, Beijing, China

15:05 - 15:25 B r e a k

SESSION 3A Synthesis for Testability
Chair: Wu-Tung Cheng
Time: 15:25 - 17:30 Room: B01

3A - 1 An Approach to the Synthesis of Synchronizable Finite
State Machines with Partial Scan, Tomoo Inoue, Toshimitsu

Masuzawa, Hiroshi Youra, Hideo Fujiwara, Nara Institute
of Science and Technology, Takayama, Ikoma, Nara, Japan

3A - 2 Waveform Polynomial Manipulation Using BDDs, Zhuxing Zhao,
Zhongcheng Li, Yinghua Min, Center for Fault-Tolerant
Computing, CAD Lab., Institute of Computing Technology,
Academia Sinica Beijing, China

3A - 3 Easily Testable Data Path Allocation Using Input/Output
Registers, Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-
Bin Liao, Dept. of Electrical Eng., NTU, Taipei, Taiwan;
Dept. of Electronic Eng., NCTU, Hsinchu, Taiwan

3A - 4 AND/EXOR Based Synthesis of Testable KFDD-Circuits with
Small Depth, Harry Hengster, Rolf Drechsler, Stefan Eckrich,
Tonja Pfeiffer, Bernd Becker, Institute of Computer Science,
Albert-Ludwigs-University, Germany; Dept. of Computer Sci.,
Johann Wolfgang Goethe Univ., Germany

3A - 5 Minimal Delay Test Sets for Unate Gate Networks, U.
H. M S.M. Reddy, Computer Science Dept., Univ. of Saarland,
Germany; Dept. of ECE, Univ. of Iowa, U.S.A.


SESSION 3B Iddq and Fault Modeling
Chair: Prab Varma
Time: 15:25 - 17:30 Room: B02

3B - 1 Two Modeling Techniques for CMOS Circuits to Enhance
Test Generation and Fault Simulation for Bridging Faults,
Kuen-Jong Lee, Jing-Jou Tang, Dept. of Electrical Eng.,
NCKU, Tainan, Taiwan

3B - 2 Algorithmic Test Generation for Supply Current Testing
of TTL Combinational Circuits, Toshimasa Kuchii, Masaki
Hashizume, Takeomi Tamesada, Dept. of Electrical and
Electronics Eng., Faculty of Eng., The Univ. of Tokushima,

3B - 3 An Efficient Compact Test Generator for IDDQ Testing,
Hisashi Kondo, Kwang-Ting Cheng, Dept. of Electrical and
Computer Eng., Univ. of California, U.S.A.

3B - 4 Realistic Linked Memory Cell Array Faults, A.J. van de Goor,
G.N. Gaydadjiev Delft Univ. of Technology, Dept. of Electrical
Eng., The Netherlands

3B - 5 On Current Testing of Josephson Logic Circuits Using the
4JL Gate Family, Teruhiko Yamada , Tsuyoshi Sasaki, Dept.
of Computer Science, Meiji Univ., Kawasaki, Japan

17:30 - 19:00 Panel Discussion

Testing of Low Power Circuits and Systems: Are There Any
Need for Special Considerations? K.-T. (Tim) Cheng, V.
Agrawal, M. Bushnell, J.-Y. Jou, K. Kinoshita, W.-Z. Shen
Organizer: Rabindra (Rob) Roy

19:00 - 21:00 Banquet

Friday November 22, 1996

08:00 - 09:00 Keynote Speech
Built-In Self-Test for Analog and Mixed-Signal Designs
(Prof. Kwang-Ting (Tim) Cheng)
Chair: Jing-Yang Jou
SESSION 4A Built-In Self-Test
Chair: Kiyoshi Furuya
Time: 09:05 - 10:45 Room: B01

4A - 1 An Efficient PRPG Strategy By Utilizing Essential
Faults, Li-Ren Huang, Jing-Yang Jou , Sy-Yen Kuo
Dept. of Electrical Eng., NTU, Taipei, Taiwan;
Dept. of Electronic Eng., NCTU, Hsinchu, Taiwan

4A - 2 DP-BIST: A Built-In Self Test For DSP DataPaths,
Saman Adham, Sanjay Gupta, Northern Telecom, P.O.
Box 3511, Station C, Ottawa, Ontario, Canada

4A - 3 A MISR Computation Algorithm for Fast Signature
Simulation, Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu
Dept. of Electrical Eng., NTHU, Hsinchu, Taiwan

4A - 4 BIST Testability Enhancement of System Level Circuits:
Experience with an Industrial Design, Kowen Lai, Christos
A. Papachristou, Dept. of Computer Eng., Case Western
Reserve Univ., U.S.A.


SESSION 4B Circuit and System Level Diagnostics
Chair: Dao-Zheng Wei
Time: 09:05 - 10:45 Room: B02

4B - 1 Low-Complexity Fault Diagnosis under the Multiple
Observation Time Testing Approach, Irith Pomeranz,
Sudhakar M. Reddy, Electrical and Computer Eng. Dept.,
Univ. of Iowa, U.S.A.

4B - 2 Efficient Multifrequency Analysis of Fault Diagnosis
in Analog Circuits Based on Large Change Sensitivity
Computation, Tao Wei, Mike W.T. Wong, Y.S. Lee, ENC
Dept, Hong Kong Polytechnic Univ. Kowloon, Hong Kong

4B - 3 A Practical Implementation of Dynamic Testing of an AD
Converter, Yuan Tzu Ting, Li Wei Chao, Wei Chung Chao
Chun Sun Institute of Science and Technology, Taoyuan,
Taiwan; Dept. of Electrical Eng., NTHU, Hsinchu, Taiwan

4B -4 Comparison Diagnosis in Large Multiprocessor Systems,
Christopher P. Fuhrman, Henri J. Nussbaumer, Industrial
Computing Lab., Dept. of Computer Sci., Swiss Federal
Institute of Technology, Lausanne, Switzerland

10:45 - 11:05 B r e a k

SESSION 5A Industrial Applications
Chair: Yuzo Takamatsu
Time: 11:05 - 12:45 Room: B01

5A - 1 Lessons Learned from Practical Applications of

BIST/B-S Technology, Najmi Jarwala, Paul W. Rutkowski,
Shianling Wu, and Chi, Lucent Technologies, Princeton,

5A - 2 Yield Improvement by Test Error Cancellation, Mill-Jer
Wang, Yen-Shung Chang, Jwu E Chen, Yung-Yuan Chen, Shaw
Cherng Shyu, The Group of Reliable Computing, Chung-Hua
Polytechnic Institute, Hsinchu, Taiwan

5A - 3 A Pragmatic, Systematic, and Flexible Synthesis for
Testability Methodology, Vladimir Castro Alves, A. Ribeiro
Antunes, Meryem Marzouki, LPC-COPPE/UFRJ, RJ, Brazil,

5A - 4 A New Model with Time Constraints for Conformance Testing
of Communication Protocols, Daisuke Teratani, Yoshiaki
Kakuda, Tohru Kikuno, Dept. of Info. and Computer Sci.,
Faculty of Eng. Sci., Osaka Univ., Japan


SESSION 5B Practical Issues
Chair: Xiaozong Yang
Time: 11:05 - 12:45 Room: B02

5B - 1 Test Generation of Analog Switched-Current Circuits,
Cheng-Ping Wang, Chin-Long Wey, Dept. of Electrical Eng.,
Michigan State Univ., East Lansing U.S.A.

5B - 2 Thermal Monitoring of Safety-Critical Integrated Systems,
V. Sz , M. Rencz , J. M. Karam, M. Lubaszewski, B. Courtois
Technical Univ. of Budapest, Dept. of Electron Devices,
Hungary ; TIMA, France

5B - 3 A New Scheme for the Fault Diagnosis of Multiprocessor
Systems, Xiaofan Yang, Tinghuai Chen, Zhongshi He, Zehan Cao,
Hongqing Cao. Computer Institute, Chongqing Univ., Chongqing,

5B - 4 On-Line Testing in Digital Neural Networks, Serge Demidenko,
Vincenzo Piuri, Electronics and Communication Eng. Dept.,
Singapore Polytechnic, Singapore; Dept. of Electronics and
Politecnico di Milano, Italy

12:45 - 13:30 L u n c h
13:30 - 17:00 Tour: Science-Based Industrial Park
(Sign up at the Registration Desk)

Saturday-Monday November 23 - 24 1996

Tour: Taroko Gorge National Park