17th Asian Test Symposium, ATS'08

[http://ats08.info.hiroshima-cu.ac.jp/] [pdf] [image]

Call For Papers
The Seventeenth Asian Test Symposium
November 24-27, 2008, Keio Plaza Hotel Sapporo, Sapporo, JAPAN

Sponsored by
IEEE Computer Society
Test Technology Technical Council
The IEICE Information and Systems Society, Technical Committee on DC
Kyushu Institute of Technology

General Co-Chairs
Yasuo Sato
Hitachi, Ltd.
Seiji Kajihara
Kyushu Institute of Technology

Program Chair
Kazumi Hatayama

Program Vice-Chair
Hiroshi Takahashi
Ehime University

Finance Chair
Yukiya Miura
Tokyo Metropolitan Uni ver si ty

Local Arrangement Chair
Masaki Hashizume
Tokushima University

Local Arrangement Vice-Chair
Hiroyuki Yotsuyanagi
Tokushima University

Registration Chair
Toshinori Hosokawa
Nihon University

Publicity Chair
Hideyuki Ichihara
Hiroshima City University

Publications Chair
Yoshinobu Higami
Ehime University

Industry Chair
Toshinobu Ono
NEC Electronics Corporation

Tutorial Chair
Michiko Inoue
Nara Institute of Science and

Audio Visual Chair
Masayuki Arai
Tokyo Metropolitan Uni ver si ty

Satoshi Ohtake
Nara Institute of Science and

North American Liaison
Krishnendu Chakrabarty
Duke University

European Liaison
Patrick Girard

Ex Offi cio
Hideo Fujiwara
Nara Institute of Science and

Call For Papers
The Seventeenth Asian Test Symposium
November 24-27, 2008, Keio Plaza Hotel Sapporo, Sapporo, JAPAN

The Asian Test Symposium (ATS) provides an international forum for engineers and
researchers from all countries of the world, especially from Asia, to present and discuss various
aspects of device, board and system testing with design, manufacturing and fi eld considerations
in mind. The offi cial language of the symposium is English. Topics of interest include, but are
not limited to:
Automatic Test Generation / Fault Simulation
Design for Testability / Synthesis for Testability
Built-In Self-Test / Test Data Compression
Delay Testing
Defect-Based Testing / IDDX Testing
Power Issues in Test
Fault Modeling & Diagnosis
Memory Test / FPGA Test
Analog and Mixed-Signal Test
RF Testing / High-Speed I/O Test
System-on-a-Chip Test
Board and System Test
Network Protocol Testing
Design Verifi cation and Validation
On-Line Test
Fault Tolerance / Dependable System
Software Testing / Software Design for Testing
Economics of Test

Regular Session: The ATS'08 Program Committee invites original, unpublished paper
submissions for ATS'08. Paper submissions should be complete manuscripts, not exceeding
six pages (including fi gures, tables, and bibliography) in a standard IEEE two-column format.
Authors should clearly explain the signifi cance of the work, highlight novel features, and
describe its current status. On the title page, please include: author name(s) and affi liation(s),
and the mailing address, phone number, fax number, and e-mail address of the contact author.
An abstract of 50 words or less and 5-10 keywords are also required. All submissions are to be
made electronically through the ATS'08 website. Detailed instructions for submissions are to be
found at the ATS'08 website. Electronic submissions in PDF fi les are strongly recommended.
The submission will be considered evidence that upon acceptance the author(s) will prepare the
fi nal manuscript (six pages for regular session) in time for inclusion in the proceedings and will
present the paper at the Symposium.
Industry Session: This session will address a wide range of practical problems in LSI test,
board and system test, diagnosis, failure analysis, design verifi cation, and so on. The session
will consist of brief oral presentations followed by poster presentations. A one-page abstract
is required for submission. Each submission should also include the complete address and
designate a contact person and a presenter. Abstract submissions should be emailed to Industry
Chair ([email protected]).

KEY DATES (Industry Session)
Submission deadline: June 23, 2008
Notifi cation of acceptance: July 11, 2008
Camera ready copy (one page): August 11, 2008

KEY DATES (Regular Session)
Submission deadline: May 19, 2008
Notifi cation of acceptance: July 11, 2008
Camera ready copy: August 11, 2008

WWW: http://ats08.info.hiroshima-cu.ac.jp

For general information: [email protected]
For submission: [email protected]
For industry session: [email protected]

Program Committee
E. Cota
D. K. Das
S. Demidenko
J. Dworak
M. Emori
D. Gizopoulos
S.-Y. Huang
T. Inoue
H. Ito
B. Kaminska
S. Kang
K. S. Kim
E. Larsson
K.-J. Lee
H. Li
E. J. Marinissen
S. Mitra
N. Mukherjee
F. Muradali
K. Nakamae
H. Nakamura
N. Nicolici
H. Okawara
Y. Okuda
S. Park
I. Pomeranz
P. Prinetto
R. Raina
S. Ravi
M. Renovell
J. Rivoir
A. Rubio
M. Sanada
S. Sasho
T. Shinogi
P. Song
M. Takakura
N. A. Touba
J. Tyszer
M. Ushikubo
A. Uzzaman
A. Wada
L.-C. Wang
S.-J. Wang
X. Wen
C.-W. Wu
H.-J. Wunderlich
D. Xiang
Q. Xu
S. Xu
T. J. Yamaguchi
K. Yamazaki
A. Yessayan
H. Yokoyama
T. Yoneda
M. Yoshida
M. Yoshimura
D. Zhao
Advance Program
Jump to 24th, 25th, 26th, 27th

Nov 24th, 2008

9:00-12:00 Tutorial 1
Statistical Screening Methods Targeting "Zero Defect" IC Quality and Reliability

13:30- 16:30 Tutorial 2
Delay Testing: Theory and Practice

Nov 25th, 2008

9:00-10:10 Plenary Session 1

9:00-9:20 Opening Remarks

9:20-9:45 Keynote Speech 1
The Value of Extending Test Solutions
Brian STEVENS (National Semiconductor - USA)

9:45-10:10 Keynote Speech 2
Architectural Evolution and Test Requirements in Digital-Convergence Era
Kunio UCHIYAMA (Hitachi - Japan)

10:40-12:00 Plenary Session 2

10:40-11:20 Invited Talk 1
The role of DFT in Yield
Brady BENWARE (Mentor Graphics - USA)

11:20-12:00 Invited Talk 2
Issues and new Scenario for Deep sub-micron LSI design and Testing
Kunihiro ASADA (Univ. of Tokyo - Japan)

13:00-14:15 Session 3A: Test Data & Response Compression

Not All Xs are Bad for Scan Compression
Anshuman CHANDRA, Rohit KAPUR (Synopsys - USA)

Evaluation of Entropy Driven Compression Bounds on Industrial Designs
Srinivasuiu ALAMPALLY (TI - India), Jais ABRAHAM (AMD - India), Rubin A. PAREKHJI (TI - India), Rohit KAPUR, T. W. WILLIAMS (Synopsys - USA)

13:00-14:15 Session 3B: Test Generation and Fault Simulation

Untestable Fault Identification in Sequential Circuits Using Model-Checking
Jaan RAIK (Tallinn Univ. of Tech. - Estonia), Hideo FUJIWARA (NAIST - Japan), Raimund UBAR, Anna KRIVENKO (Tallinn Univ. of Tech. - Estonia )

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint
Ryoichi INOUE, Toshinori HOSOKAWA (Nihon Univ. - Japan), Hideo FUJIWARA (NAIST - Japan)

LIFTING: a Flexible Open-Source Fault Simulator
Alberto BOSIO, Giorgio DI NATALE (LIRMM - France)

13:00-14:15 Session 3C: RF Testing

Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs
Hsiu-Ming CHANG (UCSB - USA), Min-Sheng LIN (Broadcom - USA), Kwang-Ting CHENG (UCSB - USA)

Low-Cost One-Port Approach for Testing Integrated RF Substrates
Abhilash GOYAL, Madhavan SWAMINATHAN (Georgia Tech. - USA)

Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems
Deuk LEE, Vishwanath NATARAJAN, R. SENGUTTUVAN, Abhijit CHATTERJEE (Georgia Tech. - USA)

15:15-16:30 Session 4A: Test Compression and BIST

Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization
Katherine Shu-Min L, Jr-Yang HUANG (National Sun Yat-Sen Univ. - Taiwan)

Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG Patterns
Nitin YOGI, Vishwani D. AGRAWAL (Auburn Univ. - USA)

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself
Jishun KUANG, Xiong OUYANG, Zhiqiang YOU (Hunan Univ. - China)

15:15-16:30 Session 4B: Test Generation for Physical Faults

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults
Sunghoon CHUN, Yongjoon KIM, Taejin KIM, Myung-Hoon YANG, Sungho KANG (Yonsei Univ. - Korea)

A Multi-Valued Algebra for Capacitance Induced Crosstalk Delay Faults
Arani SINHA (AMD - USA), Sandeep GUPTA, Melvin BREUER (USC - USA)

Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults
Yoshinobu HIGAMI (Ehime Univ.- Japan), Kewal K. SALUJA (Univ. of Wisconsin-Madison - USA), Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU (Ehime Univ. - Japan)

15:15-16:30 Session 4C: Analog and Mixed-Signal Test

Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity
Koji ASAMI (Advantest - Japan), Hidetaka SUZUKI, Hiroyuki MIYAJIMA, Tetsuya TAURA, Haruo KOBAYASHI (Gunma Univ. - Japan)

A Reduced Code Linearity Test Method for Pipelined A/D Converters
Jin-Fu LIN, Te-Chieh KUNG, Soon-Jyh CHANG (National Cheng Kung Univ. - Taiwan)

Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry
Jui-Jer HUANG (National Taiwan Univ. - Taiwan), Chuan-Che LEE (Himax Technologies - Taiwan), Jiun Lang HUANG (National Taiwan Univ. - Taiwan)

Nov 26th, 2008

9:00-10:15 Session 5A: Delay Testing

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-Cycle Paths
Thomas Edison YU, Tomokazu YONEDA, Satoshi OHTAKE, Hideo FUJIWARA (NAIST - Japan)

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths
Ming-Ting HSIEH, Shun-Yen LU, Jing-Jia LIOU (National Tsing Hua Univ. - Taiwan), Augusli KIFLI (Faraday - Taiwan)

Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay
Sean WU (UCSB - USA), Sreejit CHAKRAVARTY, Alexander TETELBAUM (LSI - USA), Li-Chung WANG (UCSB - USA)

9:00-10:15 Session 5B: Special Session: Analog Production Test 1

Effects of Advances in Analog, Mixed Signal and IO circuits on Test Strategies

Electrical Overstress Prevention & Test Best Practices
Leslie KHOO (National Semiconductor - Malaysia)

Low Distortion Sine Waveform Generation by an AWG
Akinori MAEDA (Verigy - Japan)

9:00-10:15 Session 5C: Hybrid Method for Test Data Compression

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-based Scheme
Taejin KIM, Sunghoon CHUN, Yongjoon KIM, Myung-Hoon YANG, Sungho KANG (Yonsei Univ. - Korea)

Optimizing Test Data Volume Using Hybrid Compression
Brion KELLER, Sandeep BHATIA, Thomas BARTENSTEIN, Brian Foutz, Anis UZZAMAN (Cadence - USA)

Cost Efficient Methods to Improve Performance of Broadcast Scan
Seongmoon WANG, Wenlong WEI (NEC Labs America - USA)

10:45-12:00 Session 6A: Fault Diagnosis

Hyperactive Faults Dictionary to Increase Diagnosis Throughput
Chen LIU (Univ.of Iowa - USA), Wu-Tung CHENG, Huaxing TANG (Mentor Graphics - USA), Sudhakar M. REDDY (Univ. of Iowa - USA), Wei ZOU, Manish SHARMA (Mentor Graphics - USA)

Enhancing Transition Fault Model for Delay Defect Diagnosis
Wu-Tung CHENG, Brady BENWARE, Ruifeng GUO, Kun-Han TSAI, Takeo KOBAYASHI, Kazuyuki Maruo (Mentor Graphics - USA), Michinobu NAKAO, Yoshiaki FUKUI (Renesas - Japan), Hideyuki OTAKE (Renesas Design - Japan)

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis
Fei WANG, Yu HU (ICT/CAS - China), Yu HUANG (Mentor Graphics - USA), Jing YE (Peking Univ. - China), Xiaowei LI (ICT/CAS - China)

10:45-12:00 Session 6B: Special Session: Analog Production Test 2

The HiZ problem of Power Management IC testing
Hagen GOLLER (Verigy - Germany)

Total Jitter Measurement for Testing HSIO Integrated SOCs
Takahiro YAMAGUCHI, Masahiro ISHIDA (Advantest Labs - Japan)

Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning
Fidel MURADALI (National Semiconductor - USA), Suzanne HUH, Madhavan SWAMINATHAN (Georgia Inst. of Tech. - USA)

10:45-12:00 Session 6C: Defect Based Testing

Defect Detection Rate through IDDQ for Production Testing
Junichi HIRASE (JST - Japan)

Variation Aware Analysis of Bridging Fault Testing
Urban INGELSSON, Bashir M. AL-HASHIMI (Univ. of Southampton - UK), Peter HARROD (ARM - UK)

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects
Dongok KIM, Irith POMERANZ (Purdue Univ. - USA), M. Enamul AMYEEN., Srikanth VENKATARAMAN (Intel - USA)

13:30-14:45 Session 7A: Panel: How to Increase the Effectiveness of Yield Diagnostics − Is DFM the Answer to This?

Anis Uzzaman (Cadence Design Systems, Inc. - USA)

Adit Singh (Auburn University - USA)
Srinivas Patil (Intel Corporation - USA)
Sreejit Chakravarty (LSI Corporation - USA)
Brady Benware (Mentor Graphics Corporation - USA)
Sumio Kuwabara (NEC Electronics Corporation - Japan)

13:30-14:45 Session 7B: Power Aware Test Generation

Targeting Leakage Constraints during ATPG
Goerschwin FEY (Univ. of Bremen - Germany), Satoshi KOMATSU (Univ. of Tokyo - Japan), Yasuo FURUKAWA (Advantest - Japan), Masahiro FUJITA (Univ. of Tokyo - Japan)

Power Management for Wafer-Level Test During Burn-In
Sudarshan BAHUKUDUMBI, Krishnendu CHAKRABARTY (Duke Univ. - USA)

Test Generation for State Retention Logic

13:30-14:45 Session 7C: Design for Efficient Test

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques
Chun-Kai HSU, Li-Ming DENQ, Mao-Yin WANG, Jing-Jia LIOU, Chih-Tsun HUANG, Cheng-Wen WU (National Tsing Hua Univ. - Taiwan)

On-Chip Test Generation Mechanism for Scan-Based Two Pattern Tests
Nan-Cheng LAI, Sying-Jyan WANG (National Chung-Hsing Univ. - Taiwan)

Level-Testability of Multi-Operand Adders
Nobutaka KITO, Naofumi TAKAGI (Nagoya Univ. - Japan)

15:15-17:00 Session 8A: Industry Session

System Level LBIST Implementation
Fei ZHUANG, Xiangfeng LI, Junbo JIA (Cisco Systems - China)

CooLBIST : An Effective Approach of Test Power Reduction for LBIST
Jun MATSUSHIMA, Yoichi MAEDA, Masahiro TAKAKURA (Renesas Technology Corp. - Japan)

Practical Challenges in Logic BIST Implementation - Case Studies
Shianling WU (SynTest Technologies, Inc. - USA), Hiroshi FURUKAWA (Kyushu Institute of Technology - Japan), Boryau SHEU, Laung-Terng WANG, Hao-Jan CHAO, Lizhen YU (SynTest Technologies, Inc. - USA), Xiaoqing WEN (Kyushu Institute of Technology - Japan), Michio MURAKAMI (SynTest Technologies, Inc. - USA)

USB2.0 Logic Built In Self Test Methodology
Kean Hong BOEY, Wai Mun NG, Kok Sing YAP (Intel Microelectronics (M) Sdn. Bhd. - Malaysia)

Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes
Tomonori SASAKI, Yoshiyuki NAKAMURA, Toshiharu ASAKA (NEC Electronics Corporation - Japan)

Experimental Results of Built-In JItter Measurement for Gigahertz Clock
Nai-Chen Daniel CHENG, Yu LEE, Ji-Jan CHEN (Industrial Technology Research Institute - Taiwan)

Leading Edge Technology and Test Noise
Takayuki KATAYAMA, Kou EBIHARA, Goro IMAIZUMI (Fujitsu Microelectronics Limited - Japan)

DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits
Ricky SMITH, Tony SHI (Texas Instruments - USA)

Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method
Khairul KHUSYARI, Wei Tee NG, Neal JAARSMA, Robert ABRAHAM, Peng Weng NG, Boon Hui ANG, Chin Hu ONG (Marvell Semiconductor - Malaysia)

Detectability of the Two-dimensional Detector for Time Resolved Emission Measurement
Nobuyuki HIRAI (Hamamatsu Photonics K.K. - Japan)

Protocol Aware Test Methodologies Using Today's ATE
Shawn MOLAVI, Andy EVANS, Ray CLANCY (Broadcom Corp. - USA)

15:15-16:55 Session 8B: SoC Test

Core-Level Compression Technique Selection and SOC Test Architecture Design
Anders LARSSON, Xin ZHANG, Erik LARSSON (Linko¨ping Univ. - Sweden), Krishnendu CHAKRABARTY (Duke Univ. - USA)

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
Zhiyuan HE, Zebo PENG, Petru ELES (Linko¨ping Univ. - Sweden)

A Design-for-Debug (DfD) for NoC-based SoC Debugging via NoC
Hyunbean YI (Univ. of Massachusetts - USA), Sungju PARK (Hanyang Univ. - Korea), Sandip KUNDU (Univ. of Massachusetts - USA)

Accelerated Functional Testing of Digital Microfluidic Biochips
Debasis MITRA (Indian Statistical Inst. - India), Sarmishtha GHOSHAL, Hafizur RAHAMAN (Bengal Engg. and Science Univ. - India), Bhargab B. BHATTACHARYA, D. Dutta MAJUMDER (Indian Statistical Inst. - Japan), Krishnendu CHAKRABARTY (Duke Univ. - USA)

15:15-16:55 Session 8C: Design Verification and Validation

On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation
Xiao LIU, Qiang XU (Chinese Univ. of Hong Kong - Hong Kong)

A Robust Automated Scan Pattern Mismatch Debugger
Kun-Han TSAI, Ruifeng GUO, Wu-Tung CHENG (Mentor Graphics - USA)

An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-level Designs
Yoshihisa KOJIMA, Tasuku NISHIHARA, Takeshi MATSUMOTO, Masahiro FUJITA (Univ. of Tokyo - Japan)

Coverage Directed Test Generation: Godson Experience
HaiHua SHEN, Wenli WEI, Yunji CHEN, Bowen CHEN and Qi GUO (ICT/CAS - China)

Nov 27th, 2008

9:00-10:15 Session 9A: Power Aware Scan Test

Test Power Reduction by Blocking Scan Cell Outputs
Xijiang LIN, Janusz RAJSKI (Mentor Graphics - USA)

Two-Gear Low-Power Scan Test
Chao-Wen TZENG, Shi-Yu HUANG (National Tsing-Hua Univ. - Taiwan)

DCScan: A Power-Aware Scan Testing Architecture
Gui DAI, Zhiqiang YOU, Jishun KUANG, Jiedi HUANG (Hunan Univ. - China)

9:00-10:15 Session 9B: Memory Self Test

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs
Aman KOKRADY, C.P. RAVIKUMAR (TI - India), Nitin CHANDRACHOODAN (IIT Madras - India)

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips
Yu-Jen HUANG, Jin-Fu LI (National Central Univ. - Taiwan)

A Software-Based Test Methodology for Direct-Mapped Data Cache
Yi-Cheng LIN, Yi-Ying TSAI, Kuen-Jong LEE, Cheng-Wei YEN, Chung-Ho CHEN (National Cheng Kung Univ. - Taiwan)

9:00-10:15 Session 9C: On-Line Test

Time-Multiplexed Online Checking: A Feasibility Study
Ming GAO, Hsiu-Ming CHANG, Peter LISHERNESS, Kwang-Ting CHENG (UCSB - USA)

On-Line Instruction-checking in Pipelined Microprocessors
Stefano DI CARLO (Politecnico di Torino - Italy), Giorgio DI NATALE (LIRMM - France), Riccardo MARIANI (YOGITECH - Italy)

Design of FSM with Concurrent Error Detection Based on Viterbi Decoding
Ming LI, Shiyi XU, Enjun XIA, Fayu WAN (Shanghai Univ. - China)

10:45-12:00 Session 10A: Power Aware Delay Testing

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment
Yi-Tsung LIN, Meng-Fan WU, Jiun-Lang HUANG (National Taiwan Univ. - Taiwan)

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing
Hiroshi FURUKAWA, Xiaoqing WEN, Kohei MIYASE, Yuta YAMATO, Seiji KAJIHARA (Kyushu Inst. of Tech. - Japan), Patrick GIRARD (LIRMM - France), Laung-Terng WANG (SynTest - USA), Mohammad TEHRANIPOOR (Univ. of Connecticut - USA)

Power Analysis and Reduction Techniques for Transition Fault Testing
Khushboo AGARWAL, Srinivas VOOKA, Srivaths RAVI, Rubin PAREKHJI, Arjun Singh GILL (TI - India)

10:45-12:00 Session 10B: Advanced Memory Test

Influence of Parasitic Capacitance Variations on 65nm and 32nm Predictive Model Technology SRAM Core-Cells
Stefano DI CARLO, Alessandro SAVINO, Alberto SCIONTI, Paolo PRINETTO (Politecnico di Torino - Italy)

Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault
Wan-Yu LO, Ching-Yi CHEN, Chin-Lung SU, Cheng-Wen WU (National Tsing Hua Univ. - Taiwan)

GDDR5 Training − Challenges and Solutions for ATE-based Test
Hubert WERKMANN, Dong-Myong KIM (Verigy - Germany), Shinji FUJITA (Verigy - Japan)

10:45-12:00 Session 10C: Fault Tolerance and Dependable System

A Re-design Technique of Datapath Modules in Error Tolerant Applications
Doochul SHIN, Sandeep K. GUPTA (USC - USA)

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance
Ying ZHANG, Huawei LI, Xiaowei LI (ICT/CAS - China)

Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of Dependability
Koichi BANDO, Kenji TANAKA (Univ. of Electro-Communications - Japan)