8th Workshop on RTL and High Level Testing, WRTLT'07

IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
October 12-13, 2007, Beijing Friendship Hotel, Beijing, P.R.China
Held in conjunction with the 16th Asian Test Symposium (ATS'07)
Sponsored by
IEEE Computer Society
Test Technology Technical Council
In cooperation with
Technical Committee on Fault Tolerant Computing
China Computer Federation
The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing.
WRTLT'07, the eighth workshop, will be held in conjunction with the 16th Asian Test Symposium (ATS'07) in Beijing, China. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.
Areas of interest include but are not limited to:
- Functional fault modeling - RTL ATPG
- Relationship between RTL and gate level testing - Design verification
- High level test bench generation - SoC testing
- High level approaches for testing - Microprocessor testing
Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors, 50 words abstract, keywords and the name of contact author. All submissions should be sent to the following address as Postscript or PDF attachment.
[email protected]
The submission will be considered evidence that upon acceptance the author(s) will prepare the final manuscript in time for inclusion in the digests and will present the paper at the Workshop.
Key Dates
Submission deadline: June 10, 2007
Notification of acceptance: July 24, 2007
Camera-ready copy: August 24, 2007
Workshop: October 12-13, 2007

General Co-Chair(s)
Xiaowei Li
Institute of Computing Technology, CAS

Peilin Song
Thomas J. Watson Research Center, IBM

Program Co-Chair(s)
Yu Hu
Institute of Computing Technology, CAS

Xiaoqing Wen
Kyushu Institute of Technology

Publicity Chair
Yinhe Han
Institute of Computing Technology, CAS

Publication Chair
Ke Wen
Institute of Computing Technology, CAS

Finance Chair
Jianguo Sun
Institute of Computing Technology, CAS

Local Arrangement Chair
Rong Zhang
Institute of Computing Technology, CAS

Registration Chair
Tao Lv
Institute of Computing Technology, CAS

Ex Officio
Hideo Fujiwara
Nara Institute of Science and Technology

Further Information
Email: [email protected]

Program Committee
Khader Abdel-Hafez, USA
Jinian Bian, China
Debesh K. Das, India
Toshinori Hosokawa, Japan
Hideyuki Ichihara, Japan
Michiko Inoue , Japan
Tomoo Inoue, Japan
Kazuhiko Iwasaki, Japan
Jianhui Jiang, China
Seiji Kajihara, Japan
Jisun Kuang, China
Mark Tingyu Kuo, USA
Erik Larsson, Sweden
Huawei Li, China
Chunsheng Liu, USA
Satoshi Ohtake, Japan
Ilia Polian, German
Jaan Raik, Estonia
Kewal K. Saluja, USA
Tsuyoshi Shinogi, Japan
Yihe Sun, China
Sying-Jyan Wang, Taiwan
Dong Xiang, China
Qiang Xu, Hongkong
Hiroyuki Yotsuyanagi, Japan
Dafang Zhang, China
Danella Zhao, USA

WRTLT Steering Committee
Hideo Fujiwara, Japan
Terumine Hayashi, Japan
Tomoo Inoue, Japan
Kazuhiko Iwasaki, Japan
Erik Larsson, Sweden
Xiaowei Li, China
Alex Orailoglu, USA
Kewal K. Saluja, USA
Hideo Tamamoto, Japan
Dong Xiang, China
Dafang Zhang, China


Final Program
Friday, October 12, 2007

(Meeting Room No. 3, Building 8)

Welcome Messages
WRTLT'06 Best Paper Award
Invited Talk: Modular Testing of System-on-Chip Integrated Circuits: Recent Advances and Bold Predictions.
Krishnendu Chakrabarty (Duke University, USA)

Session 1 RTL Testing
Session Chair: Kazuhiko Iwasaki (Tokyo Metropolitan University, Japan)

1.1 RTL Don't Care Path Identification and Synthesis for Transforming Don't Care Paths into False Paths
Yuki Yoshikawa1, Satoshi Ohtake, Hideo Fujiwara

1.2 An Extended Class of Acyclically Testable Circuits
Nobuya Oka, Chia Yee Ooi, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara


Coffee break & Poster Session


Session 2 Design Verification
Session Chair: Jaan Raik (Tallinn University of Technology, Estonia)

2.1 Design Verification of an embedded Processor: From Error Model to Test Method
Tao Lv, Yang Zhao, Hua-wei Li, Xiao-wei Li

2.2 Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Andre Sulflow, Ulrich kuhne, Robert Wille, Daniel Grobe, Rolf Drechsler

2.3s Accelerating Assertion Based Verification with FPGA Co-processing
Rob Quigley, Damian Dalton, Christian Steger


(First Floor, Friendship Palace)

(VIP Room, Building 8)
WRTLT Steering Committee Meeting


Session 3 Fault Tolerance and Diagnosis
Session Chair: Yu Huang (Mentor Graphics Corporation, USA)

3.1 Cost-Efficient Selection of Gates for Circuit Hardening Based on Critical Soft Error Rate
Ilia Polian, John P. Hayes, Bernd Becker

3.2 A Design-for-Diagnosis Technique for Diagnosing Integrated Circuit Faults with Faulty Scan Chains
Fei Wang, Yu Hu, Xiaowei Li


Coffee break & Poster Session


Session 4 Test Compression and BIST
Session Chair: Ilia Polian (Albert-Ludwigs-University, Germany)

4.1 Improvement in Test Compression for IP Core Testing Using Reconfigurable Network
Kazuteru Namba, Yoshikazu Matsui and Hideo Ito

4.2 A Case Study of SoC Test Resource Partitioning Using Modular Embedded Deterministic Test (EDT) Flow
David Hong, Fiona Zhou, Yu Huang, Wu Yang, Actel Niu

4.3s The Implementation Built-In Self Tests in a Digital Radio Processor (DRPTM)
Cui Mao, Deepa Mannath, Besong Val, Oren Eliezer, Scott Larson


Panel Session:

Title: Multi-Core Microprocessor Chip Verification and Test: Are They As Scalable As Design?

Organizer: Hideo Fujiwara (Nara Institute of Science and Technology, Japan)

Moderator: Alex Orailoglu (University of California - San Diego, USA)


Kazumi Hatayama (STARC, Japan)
Zainalabedin Navabi (Tehran University, Iran)
Yu Huang (Mentor Graphics Corporation, USA)
Sying-Jyan Wang (National Chung-Hsing University, Taiwan)
Krishnendu Chakrabarty (Duke University, USA)


(First Floor, Friendship Palace)

(Laoshe Tea House)
Social Event
Saturday, October 13, 2007

(Meeting Room No. 3, Building 8)

Invited Talk: Challenges and Solutions for the Design of Fault-Tolerant Systems
Zebo Peng (Linkoping University, Sweden)


Session 5 RTL Testing
Session Chair: Tomoo Inoue (Hiroshima City University, Japan)

5.1 A Test Generation Methods for State Observable FSMs to Increase Defect Coverage Under Test Length Constraint
Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwar

5.2 Register allocation scheme based on behavioral testability analysis with scheduling for easy testability
Benmao Cheng, Hong Wang, Shiyuan Yang, Daoheng Niu, Yang Jin

5.3s A New RTL Fault Model
Yiqiong Ding, Jianhui Jiang


Coffee break


Panel Session:

Title: Defect-Tolerance, Error-Tolerance: Which way to go? How?

Organizer: Qiang Xu (Chinese University of Hong Kong, China)

Moderator: Sudhakar M. Reddy (University of Iowa, USA)

Sandeep Gupta (University of Southern California, USA)
Illia Polian (Albert-Ludwigs-University, Germany)
Abhijit Chatterjee (Georgia Institute of Technology, USA)
Zebo Peng (Linkoping University, Sweden)


(First Floor, Friendship Palace)


Session 6 Design Verification and DFT
Session Chair: Rolf Drechsler (University of Bremen, Germany)

6.1 Abstraction of Word-level Polynomial Function from Arithmetic Transform for Arithmetic Datapath
Donghai Li, Guangshun Li, ,Guangsheng Ma, Jing Hu

6.2 Assertion Checking with PSL and High-Level Decision Diagrams
Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar

6.3s A Testable and Repairable Design of Continuous-Time Filters
Hu Geng, Wang Hong, Yang Shiyuan


Coffee break


Session 7 Crosstalk and Nano-Device Faults
Session Chair: Sandeep Gupta (University of Southern California, USA)

7.1 Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission
Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu

7.2 MT Compacted Set for Interconnect Crosstalk on SOC
Zhang Ying, Li Huawei, Li Xiaowei

7.3s A Fault Model for Single Electron Devices
S. Kundu, J. Mahata, S. Roy

Session 8 Scan Based Testing and ATE
Session Chair: Qiang Xu (Chinese University of Hong Kong, China)

8.1 Don't Care Filling to Reduce Leakage Power in VLSI Circuit Testing
Tapas Kr. Maiti, Santanu Chattopadhyay

8.2 Tester Structure Expression Language and Its Application to Tester Selection
Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa

8.3 On SoC Testing Using Multiple Scan Chains with Scan Tree Configurations
Hiroyuki Yotsuyanagi, Takeshi Iihara, Masaki Hashizume


Closing session

Announcement of WRTLT'08

E-mail: [email protected]