4th Workshop on RTL and High Level Testing, WRTLT'03

_____________________________________________________________________                   C A L L    F O R   P A P E R S                             WRTLT'03             4th Workshop on RTL and High Level Testing                          November 20-21,  2003 ,   Xi'an Hotel, Xi'an, P.R.China                Held in conjunction with the 12th Asian Test Symposium (ATS'03)Sponsored byIEEE Computer Society Test Technology Technical CouncilIn cooperation withTechnical Committee on Fault Tolerant Computing, China Computer Federation_____________________________________________________________________General InformationThe purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. WRTLT'03, the fourth workshop, will be held in conjunction with the 12th Asian Test Symposium (ATS'03) in Xi'an, P.R.China. It will provide anideal forum for frank discussions on this important topic of wide range, especially for coming age of system-on-a-chip (SoC) devices.Areas of interest include but are not limited to:*	Functional fault modeling*	RTL ATPG*	RTL DFT*	RTL BIST*	Relationship between RTL and gate level testing*	High level approaches for testing / verification*	SoC TestingAuthors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors,50 words abstract, keywords and the name of contact author.All submissions should be sent to the following address as Postscript or PDF [email protected] DatesSubmission deadline: August 15, 2003 (Extended)Acceptance notification : September 10, 2003Final version deadline : October 15, 2003Photocopies of accepted papers will be handed out to the attendees at the workshop site.Organizing CommitteeGeneral Chair:Xiaowei LiInstitute of Computing Technology, CASlxw(at)ict.ac.cnProgram Chair:Huawei LiInstitute of Computing Technology, CASlihuawei(at)ict.ac.cnFinance Chair:Jianguo SunInstitute of Computing Technology, CASjgsun(at)ict.ac.cnLocal Arrangement Chair:Shi WangXi'an Microelectronics Technology Inst.Registration Chair:Tao LvInstitute of Computing Technology, CASEmail: lvtao(at)ict.ac.cnProgram CommitteeMembers:Kazuhiko Iwasaki, JapanTerumine Hayashi, JapanKewal K. Saluja, USASandeep K. Gupta, USAShiyi Xu, ChinaWeikang Huang, ChinaCheng-Wen Wu, TaiwanSying-Jyan Wang, TaiwanHee Yong Youn, KoreaMatteo Sonza Reorda, ItalyTomoo Inoue, JapanZhongcheng Li, ChinaXiaowei Li, ChinaKazumi Hatayama, JapanToshinori Hosokawa, JapanDafang Zhang, ChinaYihe Sun, ChinaYingquan Zhou, ChinaWangning Long, USAXiaoming Yu, USAMichiko Inoue, JapanJianhui Jiang, ChinaJ. Paulo Teixeira, PortugalZhongwei Xu, ChinaSatochi Fukumoto, JapanWRTLT Steering CommitteeChair:Yinghua Min, ChinaMembers:Hideo Fujiwara, Japan  Xiaowei Li,China   Hideo Tamamoto, Japan   Terumine Hayashi, JapanAlex Orailoglu, USA J.Paulo Teixeira,PortugalKazuhiko Iwasaki, JapanKewal K.Saluja, USADafang Zhang, China_____________________________________________________________________Technical Program----------------------------------------------------------------------------------------------------------------------November 20----------------------------------------------------------------------------------------------------------------------Opening & Invited talk:  Extending the Reach of Hierarchical TestAlex Orailoglu - University of California, San Diego, USANovember 20, 8:30 - 9:25-----------------------------------Session 1-BISTNovember 20, 9:40 - 11:45Chair : Kewal Saluja1.1 : A Wiring-Aware Approach to Minimizing Built-In Self-Test OverheadAbdil Rashid Mohamed, Zebo Peng and Petru Eles1.2 : On the non-scan BIST schemes under power constraints for RTL data pathsZhiqiang You, Michiko Inoue, Hideo Fujiwara1.3 : On Complete Deterministic Testing Logic in BIST for High Availability systems V.Mahalingam1.4 : A RTL-level BIST Structure for a Remote Sensing Satellite ASICXiaodong Xie1.5 : Fast and Efficient Test-Point Selection Algorithm for Scan-Based BISTHu He, Yihe Sun-----------------------------------November 20, 12:00 - 13:30LunchSteering Committee Meeting (members only)-----------------------------------Session 2-ATPGNovember 20,13:30 - 15:30Chair : Michiko Inoue2.1 : An improvement of a test plan generation algorithm for hierarchical test based on strong Testability Tomoo Inoue, Naoki Okamoto, Hideyuki Ichihara, Toshinori Hosokawa, Hideo Fujiwara2.2 : VRM: Verilog RTL Model for High-Level Testing Li Shen2.3 : Verilog RTL Model Based Concurrent Fault Simulation Li Shen2.4 : Controller Testing Using Combination of GAs and Symbolic Methods Reihaneh Saberi, Elham Safi and Zainalabedin Navabi2.5 : A High-Level Testing Generation Method Based on Verilog RTL ModelYan Gao, Li Shen-----------------------------------Session 3- DFTNovember 20,15:45 - 17:50Chair : Tomoo Inoue3.1 : Random Pattern Testability of Circuits Derived from BDDsJunhao Shi, Görschwin Fey, Rolf Drechsler3.2 : An Approach to Non-Scan Design for Delay Fault Testability of Controllers Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara3.3 : Testability Analysis Algorithm of Behavioral VHDL Description Shengbing Zhang, Deyuan Gao, Ying Li3.4 : A New Low-Power Scan-Path Architecture S. Hatami, E. Atoofian, A. Afzali-Kusha and Z. Navabi3.5 : A Novel Register Allocation Method For Testability ImprovementSaeed Safari, Hadi Esmaeilzadeh, Amir Hossein Jahangir-----------------------------------BanquetNovember 20,18:30 - 20:30----------------------------------------------------------------------------------------------------------------------November  21---------------------------------------------------------------------------------------------------------------------------------------------------------Session 4- Test CompactionNovember 21,8:30 - 10:10Chair : Masaki Hashizume4.1 : On Test Data Compression Using Selective Don't-Care Identification Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, and Haruhiko Takase4.2 : Compaction Network design for Feedback-Free MISR Yinhe Han, Huawei Li, and Xiaowei Li4.3 : A Novel Partition-based Technique to Reduce the Power, Time and Data Volume in Scan-based Test Mohammad Hosseinabadi, Shervin Sharifi, Zainalabedin Navabi4.4 : Test Length Minimization under Power Constraints for Combinational CircuitsHao Wu, Zhiqiang You, Michiko Inoue, Hideo Fujiwara-----------------------------------Session 5- Functional VerificationNovember 21,10:25 - 12:00Chair : Xiaodon Xie5.1 : Property Classification for Hybrid VerificationMing Zhu , Jinian Bian, Weimin Wu, Hongxi Xue5.2 : ACSAT: A SAT Solver via Solving TSP by ACOJianzhou Zhao, Jinian Bian5.3 : Combining SystemC with Unit Test for System Level Verification of SoCYan Chen, Bo Zhou, Weidong Qiu, Chenglian Peng5.4 : A WGL Verification Approach Based on Polynomial Symbolic ManipulationsZhen-Jun Du, Guang-Sheng Ma, Gang Feng5.5 : Safety Checking By Problem Solving Weimin Wu, Di Wang, Weiwei Zheng, Jinian Bian, Ming Zhu-----------------------------------November 21,12:00 - 13:30Lunch-----------------------------------Session 6- SOC TestingNovember 21,13:00 - 15:10Chair : Weikang Huang6.1 : A New Strategy and Design For Mixed Signal SOC TestingC.V.Guru Rao, Debdeep Mukhopadhyay, D.Roy Chowdhury6.2 : A Test Access Mechanism Interfacing with IEEE 1149.1 TAP for Testing IP Based System-on-a-ChipYong-sheng Wang, Li-yi Xiao, Ming-yan Yu, Jin-xiang Wang, Yi-zheng Ye6.3 : A Genetic Testing Framework for Self-Testing of Microprocessor CoresElham Safi ,  Reihaneh Saberi and Zainalabedin Navabi6.4: Fast and Efficient Test-Point Selection Algorithm for Scan-Based BISTHu He, Yihe Sun-----------------------------------Session 7- Fault Diagnosis & On-line TestingNovember 21,15:25 - 16:40Chair : Jinian Bian7.1 : Efficient RT-level Diagnosis MethodologyOzgur Sinanoglu and Alex Orailoglu7.2 : Error Detection and Correction in VLSI Systems by complementary logic and alternating-retryJianhui Jiang7.3 : Preliminary Study Towards the EMI-Induced Bit-Flips Prediction for COTS MicroprocessorsFabian Vargas, Diogo Becker Brum, Danniel Cavalcante Lopes7.4 : A Sufficient Condition for Pessimistically t/t Diagnosable Systems with Application to Cube-Connected SystemsXiaofan Yang, Graham M. Megson-----------------------------------