11th Workshop on RTL and High Level Testing, WRTLT'10

Call for Papers [pdf][image]
Technical Program [pdf][image]




IEEE Eleventh Workshop on RTL and High Level Testing

December 5-6, 2010, 

Shanghai SHERATON Hotel, Shanghai, P.R.China


Sponsored by

IIEEE Computer Society Test Technology Technical Council


In cooperation with

Shanghai Normal University

Tongji University Tongji University

Tsing Hua University National Natural Science Foundation of China (NSFC) China Computer Federation (CCF), Committee of Fault-tolerant Computing (CFTC)



The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. The tenth workshop on RTL and high level testing (WRTLT'10) will be hold in conjunction with the 19th Asian Test Symposium (ATS'10) in Shanghai, China. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.

Areas of interest includes but not limited to:

- Functional fault modeling   


- Relationship between RTL and gate level testing

- High level test bench generation

- High level approach for testing



- Design verification

- SoC testing

- Microprocessor testing


Paper Submissions

Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should includes: title, full name and affiliation of all authors, 100 words abstract and 5 keywords. The full mailing address, phone, fax and email address of the corresponding author should be specified. All submissions must be made electronically in PDF format. Please visit our web site (http://wrtlt10.shnu.edu.cn) for full submission instructions and updated information on the workshop.

Papers will be reviewed internationally and selected based on their originality, significance, relevance, and clarity of presentation. The submissions will be considered evidence that upon acceptance the author(s) will prepare the final manuscript on time for inclusion in the digests and will present the paper at the workshop.

Important Dates

Submission deadline: July 7, 2010

Notification of acceptance: August 31, 2010

Camera-ready copy: September 30, 2010


General Chair

Jianhua Gao

Shanghai Normal University, China


Program Co-Chairs

Jianhui Jiang

TongjiUniversity, China

Jia Li

TsingHua University, China


Finance Chair

Xin Fu

Shanghai Normal University, China


Publication Chair

Chunmei Liu

Tongji University, China


Publicity Chair

Zhen Zhu

Shanghai Normal University, China


Local Arrangement Chair Jinsong Yu

Shanghai Normal University, China


Registration Chair

Xin Chen

Shanghai Normal University, China


Program Committee

Masaki Hashizume, University of Tokushima, Japan

Jinian Bian, Tsinghua University, China

Seiji Kajihara, Kyushyu Institute of Technology, Japan

Ekir Larsson, Linkoeping University, Sweden

Huawei Li, Chinese Academy of Sciences, China

Huaguo Liang, Hefei University of Technology, China

Tomokazu Yoneda, Nara Institute of Science and Technology, Japan

Yu Huang, Mentor Graphics, USA

Jing-Jia Liou, National Tsing Hua University, Taiwan

Xiaoqing Wen, Kyushu Institute of Technology, Japan

Zhiqiang You, Hunan University, China

Michiko Inoue, Nara Institute of Science and Technology, Japan

Wei Wang, Chinese Academy of Sciences, China

Hong Wang, Tsing Hua University, China

Lei Zhang, Chinese Academy of Sciences, China

Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan

Alex Orailoglu, University of California, San Diego, USA

Hideo Fujiwara, Nara Institute of Science and Technology, Japan

WRTLT Steering Committee

Chair: Xiaowei Li, China

Vice-Chair:TomooInoue, Japan

Members: Hideo Fujiwara, Japan

ToshinoriHosokawa, Japan

Kazuhiko Iwasaki, Japan

Hideo Tamamoto, Japan

Masaki Hashizume, Japan

Erik Larsson, Sweden

Alex Orailoglu, USA

Kewal K. Saluja, USA

Dong Xiang, China

Dafang Zhang, China


Technical Program

Opening Session: Invited Talks

Low-Power Testing for Low-Power Devices

Xiaoqing Wen (Kyushu Institute of Technology, Japan)

Session 1: RTL DFT

Chair: Kohei Miyase (Kyushu Institute of Technology, Japan)

S1-1 SREEP-2: SR-Equivalent Generator for Secure and Testable Scan Design

Katsuya Fujiwara, Hideo Fujiwara and Hideo Tamamoto

S1-2 Experimental Evaluation of Hybrid RTL Scan Design

Seiji Hirota, Ke Wang, Yuki Yoshikawa, Hideyuki Ichihara and Tomoo Inoue

S1-3 Testable and Built-In Self-Test Techniques for Motion Estimation Computing Arrays

Shyue-Kung Lu

S1-4 A Simulation-Based Feature Selection Approach for Test Point Selection in HDL Models

Nastaran Nemati, Seyyed Ehsan Mahmoudi, Amirhossein Simjour and Zeinalabedin Navabi

S1-5 Low-Power Wrapper Design for IP Cores Based on IEEE 1500 Standard

Yang Yu

Session 2: Design verification

Chair: Huawei Li (Institute of Computing Technology, CAS, China)

S2-1 Checking Pipelined Distributed Global Properties for Post-silicon Debug Erik Larsson,

Bart Vermeulen and Kees Goossens

S2-2 Transaction Level Formal Verification using Timed Automata

Amirali Ghofrani, Fatemeh Javaheri, Hamid Noori and Zainalabedin Navabi

S2-3 Study on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique

Masayuki Arai, Yoshihiro Tabata and Kazuhiko Iwasaki

S2-4 VPLib: A Hybrid Method to Verify Microprocessor Prototypes on FPGA

Jingfen Lu, Lingkan Gong and Peng Ma

S2-5 Test Scheduling of Modular System-on-Chip under Capture Power Constraint

Jaynarayan Tudu, Erik Larsson, Virendra Singh

Session 3: SoC testing

Chair: Yinhe Han (Institute of Computing Technology, CAS, China)

S3-1 Fast Detection and Analysis Schemes for System-in-Package in the Presence of RAM

Chia-Yi Lin, Yu-Wei Chen, Wang-Jin Chen and Hung-Ming Chen

S3-2 An Approach to Test Scheduling for Asynchronous On-Chip Interconnects Using Integer Programming

Tsuyoshi Iwagaki, Eiri Takeda and Mineo Kaneko

S3-3 Network-on-Chip Concurrent Error Recovery Using Functional Switch Faults

Naghmeh Karimi, Somayeh Sadeghi Kohan and Zainalabedin Navabi

S3-4 Test Wrapper Design for 3D System-on-Chip Using Optimized Number of TSVs

Surajit Kumar Roy, Saurav Ghosh, Hafizur Rahaman and Chandan Giri

Session 4: High level approach for testing

Chair: Jia Li (Tsing Hua University, China)

S4-1 A Practical and Efficient Method to Test for Bridging Defects

Cynthia Hao and Colin.D Renfrew

S4-2 An Optimal HDL-based Approach for Mixed-level Hierarchical Fault Simulation

Nastaran Nemati, Arezoo Kamran, MohammadHossein Sargolzaie, MohammadHashem Haghbayan and Zainalabedin Navabi

S4-3 Multi-Level Test Package, A Package for C/C++ Gate Level Fault Simulation of System Level Design

Somayeh Sadeghi Kohan, Fatemh Javaheri, Sina Mahmoodi and Zainalabedin Navabi

S4-4 An Approach for Verification Assertions Reuse in RTL Test Pattern Generation

Maksim Jenihhin, Jaan Raik, Hideo Fujiwara, Raimund Ubar and Taavi Viilukas

S4-5 Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability

Kiyonori Matsumoto, Kazuteru Namba and Hideo Ito

Session 5: Functional fault modeling, RTL ATPG & Relationship between RTL and gate level testing

Chair:  Yu Hu (Institute of Computing Technology, CAS, China)

S5-1 A New Class of Acyclically Testable Sequential Circuits with Multiplexers

Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara and Tomoo Inoue

S5-2 X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme

Kohei Miyase, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Xiaoqing Wen and Seiji Kajihara

S5-3 A Comprehensive Functional Time Expansion Model Generation Method for Datapaths

Using Controllers

Toshinori Hosokawa, Teppei Hayakawa and Masayoshi Yoshimura

S5-4 Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults

Chia Yee Ooi and Hideo Fujiwara

Session 6: Advanced Test Technology

Chair: Huaguo Liang (Hefei University of Technology, China)

S6-1 A Scalable Test Access Mechanism for Godson-T Multi-core Processor

 Luning Kong, Yu Hu and Xiaowei Li

S6-2 Low-Power DLL-based On-Product Clock Generation for 3D Integrated Circuit Testing

Michael Buttrick and Sandip Kundu

S6-3 Clock Signal Modulation for IC Electromagnetic Compatibility

Felipe Lavratti, Leticia Maria Bolzani Pöhls, Jorge Semião, Fabian Vargas, Juan Rodriguez-Andina, Isabel Teixeira and João Paulo Teixeira

S6-4 Design for Efficient Speed-Binning and Circuit Failure Prediction and Detection

Songwei Pei, Huawei Li and Xiaowei Li