4th Workshop on RTL and High Level Testing, WRTLT'03


                   C A L L    F O R   P A P E R S


             4th Workshop on RTL and High Level Testing 
                         November 20-21,  2003 ,   Xi'an Hotel, Xi'an, P.R.China             

   Held in conjunction with the 12th Asian Test Symposium (ATS'03)

Sponsored by

IEEE Computer Society Test Technology Technical Council

In cooperation with

Technical Committee on Fault Tolerant Computing, China Computer Federation


General Information

The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. 

WRTLT'03, the fourth workshop, will be held in conjunction with the 12th Asian Test Symposium (ATS'03) in Xi'an, P.R.China. It will provide anideal forum for frank discussions on this important topic of wide range, especially for coming age of system-on-a-chip (SoC) devices.
Areas of interest include but are not limited to:

*	Functional fault modeling
*	Relationship between RTL and gate level testing
*	High level approaches for testing / verification
*	SoC Testing

Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors,50 words abstract, keywords and the name of contact author.
All submissions should be sent to the following address as Postscript or PDF attachment.

Important Dates

Submission deadline: August 15, 2003 (Extended)
Acceptance notification : September 10, 2003
Final version deadline : October 15, 2003

Photocopies of accepted papers will be handed out to the attendees at the workshop site.

Organizing Committee

General Chair:
Xiaowei Li
Institute of Computing Technology, CAS

Program Chair:
Huawei Li
Institute of Computing Technology, CAS

Finance Chair:
Jianguo Sun
Institute of Computing Technology, CAS

Local Arrangement Chair:
Shi Wang
Xi'an Microelectronics Technology Inst.

Registration Chair:
Tao Lv
Institute of Computing Technology, CAS
Email: lvtao(at)ict.ac.cn

Program Committee

Kazuhiko Iwasaki, Japan
Terumine Hayashi, Japan
Kewal K. Saluja, USA
Sandeep K. Gupta, USA
Shiyi Xu, China
Weikang Huang, China
Cheng-Wen Wu, Taiwan
Sying-Jyan Wang, Taiwan
Hee Yong Youn, Korea
Matteo Sonza Reorda, Italy
Tomoo Inoue, Japan
Zhongcheng Li, China
Xiaowei Li, China
Kazumi Hatayama, Japan
Toshinori Hosokawa, Japan
Dafang Zhang, China
Yihe Sun, China
Yingquan Zhou, China
Wangning Long, USA
Xiaoming Yu, USA
Michiko Inoue, Japan
Jianhui Jiang, China
J. Paulo Teixeira, Portugal
Zhongwei Xu, China
Satochi Fukumoto, Japan

WRTLT Steering Committee
Yinghua Min, China

Hideo Fujiwara, Japan  
Xiaowei Li,China   
Hideo Tamamoto, Japan   
Terumine Hayashi, Japan
Alex Orailoglu, USA 
J.Paulo Teixeira,Portugal
Kazuhiko Iwasaki, Japan
Kewal K.Saluja, USA
Dafang Zhang, China

Technical Program
November 20
Opening & Invited talk:  Extending the Reach of Hierarchical Test
Alex Orailoglu - University of California, San Diego, USA
November 20, 8:30 - 9:25

Session 1-BIST
November 20, 9:40 - 11:45
Chair : Kewal Saluja

1.1 : A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead
Abdil Rashid Mohamed, Zebo Peng and Petru Eles

1.2 : On the non-scan BIST schemes under power constraints for RTL data paths
Zhiqiang You, Michiko Inoue, Hideo Fujiwara

1.3 : On Complete Deterministic Testing Logic in BIST for High Availability systems

1.4 : A RTL-level BIST Structure for a Remote Sensing Satellite ASIC
Xiaodong Xie

1.5 : Fast and Efficient Test-Point Selection Algorithm for Scan-Based BIST
Hu He, Yihe Sun

November 20, 12:00 - 13:30
Steering Committee Meeting (members only)

Session 2-ATPG
November 20,13:30 - 15:30
Chair : Michiko Inoue

2.1 : An improvement of a test plan generation algorithm for hierarchical test based on strong Testability
 Tomoo Inoue, Naoki Okamoto, Hideyuki Ichihara, Toshinori Hosokawa, Hideo Fujiwara

2.2 : VRM: Verilog RTL Model for High-Level Testing
 Li Shen

2.3 : Verilog RTL Model Based Concurrent Fault Simulation
 Li Shen

2.4 : Controller Testing Using Combination of GAs and Symbolic Methods
 Reihaneh Saberi, Elham Safi and Zainalabedin Navabi

2.5 : A High-Level Testing Generation Method Based on Verilog RTL Model
Yan Gao, Li Shen

Session 3- DFT
November 20,15:45 - 17:50
Chair : Tomoo Inoue

3.1 : Random Pattern Testability of Circuits Derived from BDDs
Junhao Shi, Görschwin Fey, Rolf Drechsler

3.2 : An Approach to Non-Scan Design for Delay Fault Testability of Controllers
 Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

3.3 : Testability Analysis Algorithm of Behavioral VHDL Description
 Shengbing Zhang, Deyuan Gao, Ying Li

3.4 : A New Low-Power Scan-Path Architecture
 S. Hatami, E. Atoofian, A. Afzali-Kusha and Z. Navabi

3.5 : A Novel Register Allocation Method For Testability Improvement
Saeed Safari, Hadi Esmaeilzadeh, Amir Hossein Jahangir

November 20,18:30 - 20:30

November  21

Session 4- Test Compaction
November 21,8:30 - 10:10
Chair : Masaki Hashizume

4.1 : On Test Data Compression Using Selective Don't-Care Identification
 Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, and Haruhiko Takase

4.2 : Compaction Network design for Feedback-Free MISR
 Yinhe Han, Huawei Li, and Xiaowei Li

4.3 : A Novel Partition-based Technique to Reduce the Power, Time and Data Volume in Scan-based Test
 Mohammad Hosseinabadi, Shervin Sharifi, Zainalabedin Navabi

4.4 : Test Length Minimization under Power Constraints for Combinational Circuits
Hao Wu, Zhiqiang You, Michiko Inoue, Hideo Fujiwara

Session 5- Functional Verification
November 21,10:25 - 12:00
Chair : Xiaodon Xie

5.1 : Property Classification for Hybrid Verification
Ming Zhu , Jinian Bian, Weimin Wu, Hongxi Xue

5.2 : ACSAT: A SAT Solver via Solving TSP by ACO
Jianzhou Zhao, Jinian Bian

5.3 : Combining SystemC with Unit Test for System Level Verification of SoC
Yan Chen, Bo Zhou, Weidong Qiu, Chenglian Peng

5.4 : A WGL Verification Approach Based on Polynomial Symbolic Manipulations
Zhen-Jun Du, Guang-Sheng Ma, Gang Feng

5.5 : Safety Checking By Problem Solving
 Weimin Wu, Di Wang, Weiwei Zheng, Jinian Bian, Ming Zhu

November 21,12:00 - 13:30

Session 6- SOC Testing
November 21,13:00 - 15:10
Chair : Weikang Huang

6.1 : A New Strategy and Design For Mixed Signal SOC Testing
C.V.Guru Rao, Debdeep Mukhopadhyay, D.Roy Chowdhury

6.2 : A Test Access Mechanism Interfacing with IEEE 1149.1 TAP for Testing IP Based System-on-a-Chip
Yong-sheng Wang, Li-yi Xiao, Ming-yan Yu, Jin-xiang Wang, Yi-zheng Ye

6.3 : A Genetic Testing Framework for Self-Testing of Microprocessor Cores
Elham Safi ,  Reihaneh Saberi and Zainalabedin Navabi

6.4: Fast and Efficient Test-Point Selection Algorithm for Scan-Based BIST
Hu He, Yihe Sun

Session 7- Fault Diagnosis & On-line Testing
November 21,15:25 - 16:40
Chair : Jinian Bian

7.1 : Efficient RT-level Diagnosis Methodology
Ozgur Sinanoglu and Alex Orailoglu

7.2 : Error Detection and Correction in VLSI Systems by complementary logic and alternating-retry
Jianhui Jiang

7.3 : Preliminary Study Towards the EMI-Induced Bit-Flips Prediction for COTS Microprocessors
Fabian Vargas, Diogo Becker Brum, Danniel Cavalcante Lopes

7.4 : A Sufficient Condition for Pessimistically t/t Diagnosable Systems with Application to Cube-Connected Systems
Xiaofan Yang, Graham M. Megson