19th Asian Test Symposium, ATS'10‬

Call for Papers [pdf][image]
Advance Program [pdf][image]
The 19th Asian Test Symposium

December 1-4, 2010, Sheraton Hotel, Shanghai, China
Sponsored by

IEEE Computer Society & Shanghai University

In Cooperation With

Shanghai Normal University National Natural Science Foundation of China (NSFC) China Computer Federation (CCF), Committee of Fault-tolerant Computing (CFTC)

General Chair:

Shiyi Xu

Shanghai University (China)


Program Co-Chairs:

Jianhua Gao

Shanghai Normal University (China)

Yasuo Sato

Kyushu Institute of Technology(Japan)


Tutorial Chair:

Jianhui Jiang

Tongji University (China)


Finance Chair:

Hua Liu

Shanghai University (China)


Publication Chair:

Quan Qian

Shanghai University (China)


Publicity Chair:

Rui Zhang

Shanghai University (China)


Local Arrangement Chair:

Xin Fu

Shanghai Normal University (China)


Registration Chair:

Junjie Peng

Shanghai University (China)


ATS Steering Committee Chair:

Seiji Kajihara

Kyushu Institute of Technology(Japan)


Program Committee:

Jacob A Abraham (USA)

Vishwani Agrawal (USA)

Jean Arlat (France)

Krishnendu Chakrabarty (USA)

Krishna Chakravadhanula (USA)

Debesh K Das (India )

Kiyoshi Furuya (Japan)

Jianhua Gao (China)

Patrick Girard (France)

Sandeep Gupta (USA)

Masaki Hashizume (Japan)

Kazumi Hatayama (Japan)

Hiromi Hiraishi (Japan)

Michael Hobbs (Australia)

Michael S. Hsiao (USA)

Yu Hu (China)

Chih-Tsun Huang (Taiwan)

Jiun-Lang Huang (Taiwan)

Shi-Yu Huang (Taiwan)

Yu Huang (USA)

Michiko Inoue (Japan)

Tomoo Inoue (Japan)

Kazuhiko Iwasaki (Japan)

Jianhui Jiang (China)

Seiji Kajihara (Japan)

Sungho Kang (Korea)

Rohit Kapur (USA)

Tohru Kikuno (Japan)

Jishun Kuang (China)

Erik Larsson (Sweden)

Kuen-Jong Lee (Taiwan)

Huawei Li (China)

Katherine Shu-Min Li (Taiwan)

Huaguo Liang (China)

Shyue-Kung Lu (Taiwan)

Michael Lyu (Hong Kong)

Erik Jan Marinissen (Belgium)

Huaikou Miao (China)

Subhasish Mitra (USA)

Fidel Muradali (USA)

Satoshi Ohtake (Japan)

Jehan-François Pâris (USA)

Zebo Peng (Sweden)

Ilia Polian (Germany)

Irith Pomeranz (USA)

Sudhakar M Reddy (USA)

Michel Renovell (France)

Kewal K. Saluja (USA)

Indranil Sengupta (India)

Peilin Song (USA)

Chauchin Su (Taiwan)

Hiroshi Takahashi (Japan)

Nur A. Touba (USA)

Marco Vieira (Portugal)

Sying-Jyan Wang (Taiwan)

Li-C. Wang (USA)

Seongmoon Wang (USA)

Xiaoqing Wen (Japan)

Yue Wu (China)

Cheng-Wen Wu (Taiwan)

Qiang Xu (Hong Kong)

Xiaozong Yang (China)


Call For Papers

The 19th Asian Test Symposium

December 1-4, 2010, Sheraton Hotel, Shanghai, China


ATS 2010 is the nineteenth in this series of symposia started in 1992 that are devoted to testing and fault tolerant computing. ATS is now recognized as the main regular event of the word that is covering the many dimensions of Testing for computing systems. The symposium will be organized by the Shanghai University, Shanghai, the most modernized city of China. Shanghai is a vibrant blend of traditional culture and cosmopolitan life and it is the economic, educational and recreational center of the country, offering a variety of significant cultural sights. The famous 2010 World Expo will be held in Shanghai where a number of brilliant buildings and exhibition halls in different styles will be shown to the world.


Following the traditions set up by its predecessors, this year ATS 2010 aims at providing a more open forum for worldwide researchers and industrial practitioners to exchange their innovative ideas on testing technology for both hardware and software in computing systems. ATS 2010 will stress its theme on the “New development and applications of testing technology”, covering all aspects of technical issues on design-for-testability, test integration, diagnosis, repair, and yield enhancement of a complex chip with embedded digital, analog, and/or memory components.


Original contributions on VLSI testing are solicited. Topics of interest include, but are not limited to, the following categories:

1. Test generation & fault simulation 3. Fault diagnosis 5. Memory testing and FPGA testing 7. Delay fault testing / Low power testing 9. System-on-a-chip- test/ System-in-package test 11. Software testing / verification

13. Failure analysis / fault modeling 15. Fault tolerance / error correction 17. IDDQ testing 19. Test standard: IEEE 1500, boundary scan 21. Automatic test equipment

Paper Submissions:

2. DfX: Design for testability, reliability, dependability... 4. Analog & mixed-signal testing / RF/ High speed I/O testing 6. Wafer-level testing 8. Board and system testing / On-line testing 10. Network-on-a-chip testing 12. CPU testing 14. Built-in self-test / Embedded testing 16. Functional testing 18.    T est     economics 20. Test experience in industry 22. Yield Enhancement / Silicon debug

Manuscripts should be submitted in the following categories: Regular Papers and Practical Experience Reports. Regular Papers should describe original research (not submitted or published elsewhere) and be not more than 20 double-spaced pages including figures and tables using 11- point type. Practical Experience Reports (of 5-12 pages) should describe an experience or a case study, such as the design and deployment of a system or actual failure and recovery field data. The title page should include a 150-word abstract, five keywords, authors’ names and affiliations and a line specifying whether the submission is a Regular Paper or a Practical Experience Report. The full mailing address, phone, fax and email address of the corresponding author should be specified. All submissions must be made electronically (in PDF format) on web site (http://ats10.shu.edu.cn). Please visit our web site for full submission instructions and updated information on the symposium.

Papers will be reviewed internationally and selected based on their originality, significance, relevance, and clarity of presentation. All accepted papers will be published in ATS Proceedings by IEEE Computer Society Conference Publication Service (CPS) and will be EI and ISTP indexed.



Important Dates Due

Submission: May 24th 2010;

Notification: July 14th 2010;

Final Version: August 18th 2010

Tutorial: December 1st, 2010 ;

Symposium: December 2nd, 2010



Technical Program


Dec. 01, 2010

Registration (9:00-20:30) and Tutorial (13:00-17:30)

Dec. 02, 2010

Session 1: Opening Session

Session Chair: Dec. 02, 8: 45 – 9: 30

Session 2: Plenary Session (Keynote Speech)

Session Chair: Dec. 02, 9:50 – 11:50

Keynote Speech (1)

Speaker    To be decided soon


Keynote Speech (2)

Speaker    To be decided soon

Session 3A:       Analog & Mixed-Signal testing / RF/ High Speed I/O Testing


Session Chair: Dec. 02, 13:00-15:00

Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Single Sine wave Modulated RF Stimulus

Authors     Shreyas Sen, Shyam Devarakond and Abhijit Chatterjee

Title Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures

Authors     Shyam Kumar Devarakond, Shreyas Sen, Vishwanath Natarajan, Aritra Banerjee, Hyun Choi, Ganesh Srinivasan and Abhijt Chatterjee


The Test Ability of an Adaptive Pulse Wave for ADC Testing

Authors     Xiaoqin Sheng and Hans Kerkhoff


Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation

Authors     Ke Huang, Haralampos-G. Stratigopoulos and Salvador MirTitle

Session 3B:       System-on-a-Chip Test / System-in-Package Test

Session Chair: Dec. 02, 13:00-15:00

A Test Integration Methodology for 3D Integrated Circuits

Authors Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou and Cheng-Wen Wu


Application-Aware Online Testing for Many-Core SoC

Authors     Jason Lee, Suman Mandal and Rabi Mahapatra


Performance Characterization of TSV in 3D IC via Sensitivity Analysis

Authors     Jhih-wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou and Cheng-Wen Wu


Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation

Authors     Nima Aghaee, Zhiyuan He, Zebo Peng and Petru Eles


Session 3C: Special Session for Doctoral Contest

Session Chair: Dec. 02, 13:00-15:00

Reports will be delivered in this Session

See detail information of Doctoral Contest


Session 4A: Automatic Test Equipment & Memory and FPGA Testing

Session Chair: Dec. 02, 15:20-17:20

Title At-speed Test of High-speed DUT using Built-off Test Interface

Authors Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob Abraham, Eonjo Byun, Cheol-Jong Woo and Sejang Oh


Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing

Authors Krishna Kumar S, S. Kaundinya and Santanu Chattopadhyay


New Microcode’s Generation Technique for Programmable Memory Built-In Self Test

Authors Nur Qamarina Mohd Noor, Azilah Saparon, Yusrina Yusof and Mahmud Adnan

Title *A Smart RTL Verification System for Internal Signal Probing and Behavior Trace

Authors Yu-lin Wang, Chung-Ping Young and Alvin W.Y. Su


Session 4B: Low Power Testing

Session Chair: Dec. 02, 15:20-17:20

Adaptive Low Shift Power Test Pattern Generator for Logic BIST

Authors Xijiang Lin and Janusz Rajski


Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-Speed Scan Testing

Authors Chun-Yong Liang, Meng-Fan Wu and Jiun-Lang Huang


Modified Scan Flip-Flop for Low Power Testing

Authors Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty and Adit Singh


Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power

Authors Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang and Hideo Fujiwara


Session 4C:       Software Testing and Reliability Model

Session Chair: Dec. 02, 15:20-17:20

Tackling the Path Explosion Problem in Symbolic Execution-driven Test Generation for Programs

Authors Saparya Krishnamoorthy, Michael Hsiao and Loganathan Lingappan


A Reliability Model for Object-Oriented Software

Authors Peng Xu and Shiyi Xu


A New Approach to Generating High Quality Test Cases

Authors Pan Liu and Huaikou Miao


A Study on Software Reliability Prediction Based on Transduction Inference

Authors Jun-Gang Lou, Jian-Hui Jiang, Chun-Yan Shuai and Ying Wu


Dec. 03, 2010

Session 5A:       Board and System Testing / On-line Testing

Session Chair: Dec. 03, 08:30-10:00

Software-Based Self-Testing of Processors Using Expanded Instructions

Authors Ying zhang, Huawei Li and Xiaowei Li


Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures

Authors     Hongxia Fang, Zhiyuan Wang, Xinli Gu and Krishnendu Chakrabarty


Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test

Authors     Zhaobo Zhang, Zhanglei Wang, Xinli Gu and Krishnendu Chakrabarty

Session 5B:       Test Generation & Fault Simulation (1)

Session Chair: Dec. 03, 08:30-10:00

Title Efficient Simulation of Structural Faults for the System Reliability Evaluation at System Level

Authors     Michael Kochte, Christian Zoellin, Rafal Baranowski, Michael Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo and Paolo Prinetto


Jitter Characterization of Pseudo-Random Bit Sequences Using Incoherently Sub-Sampling

Authors     Hyun Choi and Abhijit Chatterjee


On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

Authors     Xiang Fu, Huawei Li and Xiaowei LI


Session 5C:       Failure Analysis / Fault Modeling (1)

Session Chair: Dec. 03, 08:30-10:00

Variation-Aware Fault Modeling

Authors Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren and Hans-Joachim Wunderlich


Diagnosis of Multiple Physical Defects Using Logic Fault Models

Authors     Xun Tang, Wu-Tung Cheng, Ruifeng Guo and Sudhakar Reddy


A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

Authors     Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel and L. Dilillo


Session 6A: Built-in Self-Test / Embedded Testing (1)

Session Chair:

Dec. 03, 10:20-12:00

A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces

Authors     Hyunjin Kim and Jacob A. Abraham

Title A Complete Logic BIST Technology with No Storage Requirement

Authors     Wei-Cheng Lien and Kuen-Jong Lee

Title Efficient embedding of deterministic test data

Authors Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson and Erik Larsson

Session 6B:       Test Generation & Fault Simulation (2)

Session Chair: Dec. 03, 10:20-12:00

Title FSimGP2: An Efficient Fault Simulator with GPGPU

Authors     Min Li and Michael Hsiao

Title A Quasi-Best Random Testing

Authors     Shiyi Xu and Peng Xu

Title Design of DSP virtual machine oriented all-digital simulation and testing

Authors     Chongwen Wang and Gangyi Ding

Title Formula-Oriented Compositional Minimization in Model Checking

Authors     Bowen Chen, Haihua Shen and Wenhui Zhang

Session 6C:       Failure Analysis / Fault Modeling (2)

Session Chair: Dec. 03, 10:20-12:00

Title On Soft Error Immunity of Sequential Circuits

Authors     Dan Zhu, Tun Li and SiKun Li

Title Testing of Digital Microfluidic Biochips using Improved Eulerization Techniques and the Chinese Postman Problem

Authors Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty and Bhargab B Bhattacharya.


P2CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework

Authors     Song Jin, Yinhe Han, Huawei Li and Xiaowei Li


Afternoon Tour in Shanghai (13:00 — 18:00)

Night Banquet (18:30 — 21:00)

Dec. 04, 2010

Session 7A: Built-in Self-Test / Embedded Testing (2)

Session Chair: Dec. 04, 08:30-10:00

Built-in Self-Test for Capacitive MEMS using a Charge Control Technique

Authors Iftekhar Ibne Basith, Nabeeh Kandalaft and Rashid Rashidzadeh


Defect Coverage-Driven Window-Based Test Compression

Authors Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros and Vasileios Tenentes


Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code

Authors Masashi Ishikawa, Hiroyuki Yotsuyanagi and Masaki Hashizume


Session 7B:       Test Generation & Fault Simulation (3)

Session Chair: Dec. 04, 08:30-10:00

Testing of Low-Cost Digital Microfluidic Biochips with Non-Regular Array Layouts

Authors Yang Zhao and Krishnendu Chakrabarty


Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits

Authors Dipak K. Kole, Hafizur Rahaman, Debesh K Das and Bhargab B. Bhattacharya


On Determining the Real Output Xs by SAT-Based Reasoning

Authors Melanie Elm, Michael Kochte and Hans-Joachim Wunderlich

Title * Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

Authors Mohammad Hashem Haghbayan, Sara Karamati, Fatemeh Javaheri and Zanalabedin Navabi

Session 7C:       DFX: Design for Testability, Reliability, Dependability... (1)


Session Chair: Dec. 04, 08:30-10:00

Pattern Encodability Enhancements for Test Stimulus Decompressors

Authors Nader Alawadhi, Ozgur Sinanoglu and Mohammed Al-Mulla


High Performance Compaction for Test Responses with Many Unknowns

Authors Thomas Rabenalt, Michael Richter and Michael Goessel


Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs

Authors Yizi Xing and Liquan Fang


Session 8A:       Built-in Self-Test / Embedded Testing (3)

Session Chair: Dec. 04, 10:20-12:00

Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST

Authors     Hiroshi Yokoyama, Hideo Tamamoto and Kewal K. Saluja


Parallel LFSR Reseeding With Selection Register For Mixed-Mode BIST

Authors Piyanart Kongtim and Taweesak Reungpeerakul


On-chip Jitter Measurement Using Vernier Ring Time-to-digital Converter

Authors JianjunYuandFaDai


Session 8B:       Yield Enhancement / Silicon Debug (1)

Session Chair: Dec. 04, 10:20-12:00

HYPERA: High-Yield Performance-Efficient Redundancy Analysis

Authors Tsung-Chu Huang, Kuei-Yeh Lu and Yen-Chieh Huang


A Comprehensive System-on-Chip Logic Diagnosis

Authors Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel and Olivia Riewer


On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

Authors Xiao Liu and Qiang Xu

Session 8C: DFX: Design for Testability, Reliability, Dependability...(2)


Session Chair: Dec. 04, 10:20-12:00

Substantial Fault Pair at A Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Authors     Jing Ye, Xiaolin Zhang, Yu Hu and Xiaowei Li


D-Scale: A Scalable System-level Dependable Method for MPSoCs

Authors Nicolas Hebert, Pascal Benoit, Gilles Sassatelli and Lionel Torres


Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits

Authors Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara


Session 9A:       Delay Fault Testing (1)

Session Chair: Dec. 04, 13:00-14:50

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test

Authors Wei Zhao, Junxia Ma, Mohammad Tehranipoor and Sreejit Chakravarty


Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Authors Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng and Mohammad Tehranipoor


Seed Ordering and Selection for High Quality Delay Test

Authors TomokazuYoneda,MichikoInoue,AkiraTaketaniandHideoFujiwara


On Bias in Transition Coverage of Test Sets for Path Delay Faults

Authors Irith Pomeranz and Sudhakar Reddy


Session 9B:       Yield Enhancement / Silicon Debug (2)

Session Chair: Dec. 04, 13:00-14:50

HYPER: A Heuristic for Yield/Area Maximizing Improvement using Redundancy in SoC

Authors Mohammad Mirza-Aghatabar, Melvin Breuer and Sandeep Gupta


Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking

Authors Wu-TungChengandYuHuang


Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure

Authors Chih-Yun Pai and Shu-Min Li

Session 9C: DFX: Design for Testability, Reliability, and Dependability... (3)


Session Chair: Dec. 04, 13:00-14:50

XOR-Based Response Compactor Adaptive to X-Density Variation

Authors Samah Saeed and Ozgur Sinanoglu


DFT + DFD: An Integrated Method for Design for Testability and Diagnosability

Authors Nikhil Rahagude, Maheshwar Chandrasekar and Michael Hsiao


Thermal Safe High Level Test Synthesis for Hierarchical Testability

Authors Tung-HuaYehandSying-JyanWang


Accelerating Strategy for Functional Test of NoC Communication Fabric

Authors Yan Zheng, Hong Wang, Shiyuan Yang, Chen Jiang and Feiyu Gao


Session 10A:     Delay Fault Testing (2)

Session Chair: Dec. 04, 15:10-17:10

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths

Authors Zijian He, Tao Lv, Huawei Li and Xiaowei Li


Distinguishing Resistive Small Delay Defects from Random Parameter Variations

Authors Xi Qian and Adit D. Singh


A Low Area On-Chip Delay Measurement System Using Embedded Delay Measurement Circuit

Authors Kentaroh Katoh, Kazuteru Namba and Hideo Ito

Title A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection

Authors     Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty and Mohammad Tehranipoor

Session 10B:     Test Economics / Functional Verification / Failure Analysis


Session Chair: Dec. 04, 15:10-17:10

Test Cost Analysis for 3D Die-to-Wafer Stacking

Authors Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker and Erik Jan Marinissen


Mining Complex Boolean Expressions for Sequential Equivalence Checking

Authors Neha Goel, Michael Hsiao, Naren Ramakrishnan and Mohammed Zaki


On-the-fly Reduction of Stimuli for Functional Verification

Authors QiGuo,TianshiChen,HaihuaShen,YunjiChenandWeiwuHu


Test Time Analysis for IEEE P1687

Authors Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson

l The Advance Program is subject to change without notice until a Final Program is released.

l Papers with an asterisk “*” had not been submitted to IEEE CPS before Sept. 9, 2010.