[http://ats06.cs.ehime-u.ac.jp]
------------------------------------------------------------------------
Call For Papers
ATS'06
The Fifteenth Asian Test Symposium
November 20-23, 2006, Software Research Park, Fukuoka, JAPAN
Sponsored by
IEEE Computer Society
Test Technology Technical Council
Technical Group on Dependable Computing, IEICE
Kyushu Institute of Technology
SCOPE
The Asian Test Symposium (ATS) provides an international forum for engineers and researchers
from all countries of the world, especially from Asia, to present and discuss various aspects
of system, board and device testing with design, manufacturing and field considerations in
mind. The official language of the symposium is English. Topics of interest include, but are
not limited to:
Automatic Test Generation / Fault Simulation
Synthesis for Testability / Design for Testability
Built-In Self-Test / On-line Testing
Software Testing / Software Design for Testing
Fault Modeling & Diagnosis
Mixed-Signal Test
Network Protocol Testing
Design Verification
Electron-Beam Testing
Economics of Test
Fault Tolerance
IDDQ Test
System-on-Chip Test
SUBMISSIONS
Regular session: The ATS’06 Program Committee invites original, unpublished paper
submissions for ATS’06. Paper submissions should be complete manuscripts, not extending
six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column
format. Authors should clearly explain the significance of the work, highlight novel features,
and describe its current status. On the title page, please include: author name(s) and
affiliation(s), and the mailing address, phone number, fax number, and e-mail address of
the contact author. A 50-words abstract and five keywords are also required.
All submissions are to be made electronically through the ATS’06 website. Detailed instructions
for submissions are to be found at the ATS’06 website. Electronic submissions (PDF or PS
files) are strongly recommended. In case of hardcopy submission one should contact to
Program Chair for special instructions.
The submission will be considered evidence that upon acceptance the author(s) will prepare
the final manuscript (six pages for regular session) in time for inclusion in the proceedings
and will present the paper at the Symposium.
Industry session: This session will address a wide range of practical problems in LSI test,
board and system test, diagnosis, failure analysis, design verification, and so on. This
session will consist of brief presentations followed by poster presentations. A one-page
abstract is required for submission. Each submission should also include the complete
address and designate a contact person and a presenter. All submission should be mailed to
Industrial Arrangement Chair (industrial(at)aries30.cse.kyutech.ac.jp).
KEY DATES (Regular session) KEY DATES (Industry session)
Submission deadline: May 10, 2006 Submission deadline: June 23, 2006
Notification of acceptance: July 10, 2006 Notification of acceptance: July 10, 2006
Camera ready copy: August 10, 2006 Camera ready final manuscript
Symposium: November 20-23, 2006 (one-page abstract): August 10, 2006
General Chair
Hiromi Hiraishi
Kyoto Sangyo University
General Vice-Chair
Hideo Tamamoto
Akita University
Program Chair
Seiji Kajihara
Kyushu Institute of
Technology
Tutorial Chair
Takashi Aikyo
Semiconductor Technology
Academic Research Center
Publicity Chair
Hiroshi Takahashi
Ehime University
Publications Chair
Toshinori Hosokawa
Nihon University
Finance Chair
Tomoo Inoue
Hiroshima City University
Local Arrangement Chair
Hiroshi Date
System JD Co., Ltd.
Registration Chair
Satoshi Ohtake
Nara Institute of Science
and Technology
Industrial Arrangement Chair
Kazumi Hatayama
Semiconductor Technology
Academic Research Center
Audio Visual Chair
Yukihiro Iguchi
Meiji University
Secretary
Yukiya Miura
Tokyo Metropolitan
University
North American Liaison
Alex Orailoglu
University of California,
San Diego
European Liaison
Michel Renovell
LIRMM
Ex Officio
Hideo Fujiwara
Nara Institute of Science
and Technology
Program Committee
J. Abraham, V. D. Agrawal, K. Chakrabarty, T. T. Cheng, W.-T. Cheng, D. R. Chowdhury, S. Demidenko, P. Girard, M. Hashizume,
Y. Higami, S.Y. Huang, L. Huawei, H. Ichihara, M. Inoue, H. Itoh, A. Ivanov, K. Iwasaki, S. Kang, C. Landrault, E. Larsson,
C.-L. Lee, K.-J. Lee, X. Li, E. J. Marinissen, F. Muradali, Z. Navabi, Y. Okuda, N. Otsuka, P. P. Chaudhuri, I. Polian, P. Printetto,
J. Rajski, R. Rajsuman, S. M. Reddy, A. Rubio, K. K. Saluja, Y. Sato, T. Shinogi, C.C. Su, A. Uzzaman, X. Wen, TW Williams,
C.-W. Wu, S. Xu, T. Yamaguchi, M. Yoshida, M. Yoshimura
---------------------------------------------
Final Program
November 20
Tutorial 1
8:30-11:30
Delay Testing: Theory and Practice
Srinivas Patil (Intel - USA)
Nandu Tendolkar (Freescale Semiconductor - USA)
Tutorial 2
13:30-16:30
Memory Test and Self-Test for Deep Sub-micron Technologies
R. Dean Adams (Magma Design Automation -USA)
top
Reception
18:00-21:00 at SRP
November 21
1A Opening session
8:30-9:45
Welcome Message: Hiromi Hiraishi, General Chair
PC Chair's Message: Seiji Kajihara, Program Chair
Keynote Address: Pau; D. Roddy (OAI Technical Manager, Advantest America, USA)
Invited Keynote Address: Hiroto Yasura (Professor, Kyushu University)
Session 2A: Test power reduction
10:15-11:30
Chair: T. W. Williams (Synopsys, USA )
2A.1 Power-Aware Test Data Compression for Embedded IP Cores
N. Badereddine (LIRMM - France), Z. Wang (Duke Univ. - USA), P. Girard (LIRMM - France), K. Chakrabarty (Duke Univ. - USA), A. Virazel (LIRMM - France), S.Pravossoudovitch (LIRMM - France), C. Landrault (LIRM - France)
2A.2 Scan Chain Adjustment Technology for Test Power Reduction
J. Li(Institute of Computing Technology - China), Y. Hu (Chinese Academy of Sciences - China), X. Li (Chinese Academy of Sciences - China)
2A.3 TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure
Y. Kim, D. Song, K. Kim, I. Kim, S. Kang (Yonsei Univ.- Korea)
Session 2B: Memory test
10:15-11:30
Chair: H. Tamamoto (Akita Univ., Japan
2B.1 An Enhanced SRAM BISR Design with Reduced Timing Penalty
L.-M. Denq, T.-C. Wang, C.-W. Wu (National Tsing Hua Univ. - Taiwan)
2B.2 Memory Fault Simulator for Static-Linked Faults
A. Bosio, A. Benson, S. D. Carlo, G. D. Natale, P. Prinetto (Politecnico di torino - Italy)
2B.3 Test/Repair Area Overhead Reduction for Small Embedded SRAMs
B. Wang (ATI Technologies Inc - Canada), Q. Xu (The Chinese University of Hong Kong - Hong Kong)
Session 2C: Test techniques
10:15-11:30
Chair: M. Hashizume (Univ. of Tokushima , Japan )
2C.1 Statistical Linearity Calibration of Time-To-Digital Converters Using A Free-Running Ring Oscillator
J. Rivoir (Verigy Germany GmbH - Germany)
2C.2 Histogram Based Testing Strategy for ADC
H.-W. Ting, B.-D. Liu, S.-J. Chang (National Cheng Kung University - Taiwan)
2C.3 Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application
Y. Miura (Tokyo Metropolitan Univ. - Japan)
Session 3A: IDDQ and burn-in test
13:30-14:45
Chair: Y. Okuda (SONY, Japan)
3A.1 Delta-IDDQ Testing of Resistive Short Defects
P. Engelke (Albert-Ludwigs-Univ. - Germany), I. Polian (Albert-Ludwigs-Univ. - Germany), H. Manhaeve (Q-Star Test, - Belgium), M. Renovell (LIRMM - France), B. Becker (Albert-Ludwigs-Univ. - Germany)
3A.2 A BIC Sensor Capable of Adjusting IDDQ Limit in Tests
M. Nakanishi, M. Hashizume, H. Yotsuyanagi (Univ. of Tokushima - Japan), Y. Miura (Tokyo Metropolitan Univ. - Japan)
3A.3 ATPG For Dynamic Burn-In Test in Full-Scan Circuits
A. Benso, A. Bosio, S. Di Carlo, G. D. Natale, P. Prinetto, (Politecnico di Torino - Italy)
Session 3B: High-level test
13:30-14:45
Chair: W.-T. Cheng (Menter Graphics, USA)
3B.1 Spectral RTL Test Generation for Gate-Level Stuck-at Faults
N. Yogi , V. Agrawal (Auburn Univ. - USA)
3B.2 An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains
T. Lv (Chinese Academy of Sciences - China), L. Liu (Chinese Academy of Sciences - China), Y. Zhao (Tsinghua Univ. - China), H. Li (Chinese Academy of Sciences - China), X. Li (Chinese Academy of Sciences - China)
3B.3 A Functional Fault Model with Implicit Fault Effect Propagation Requirements
I. Pomeranz (Purdue Univ.- USA), S. Patil (Intel - USA), P. Parvathala (Intel - USA)
Session 3C:Design verification
13:30-14:45
Chair: S. Kimura (Waseda Univ., Japan)
3C.1 The Potential and Limitation of Probabilistic Equivalence Checking
C.-Y. Wang, S.-C. Wu, J.-A. Hsieh (National Tsing Hua Univ. - Taiwan)
3C.2 Verification Methodology for Self-Repairable Memory System
J.-F. Li, C.-H. Wu (National Central Univ. - Taiwan)
3C.3 A Soft Error Tolerant LUT Cascade Emulator
H. Nakahara, T. Sasao (Kyushu Institute of Technology - Japan)
November 21
Sumo tour
15:00-18:00
Banquet
19:00-21:00 at JAL Resort Sea Hawk Hotel Fukuoka
top
November 22
Session 4A: Special session
8:30-9:45
Chair: K. Hatayama (Semiconductor Technology Academic Research Center: STARC, Japan )
Keynote: To Overtest Or Not To Overtest - More Questions Than Answers
I. Pomeranz
Industry (Short-Presentation)
1. How to perform DFT timing in mixed signal designs, from 28 hours to 7 minutes
J. Jiang, P. Wong (Rambus - USA)
2. An application of IDD spectrum testing method to the fault analysis
K. Sakaguchi (NEC Electronics - Japan)
3. iDEN(tm) Phone System Test: An Automation Approach
M. A. Mazlan, O. K. Wei, C. P. Sim (Motorola GSG Penang - Malaysia )
4. Development of practical ATPG tool with flexible interface
M. Yoshimura (FLEETS - Japan), Y, Matsunaga (Kyushu Univ. -Japan)
5. Mentor Graphics DFT to Navigate Nanometer Test Challenges
G. Aldrich, R. Press, T. Kobayashi, T. Sakajiri (Mentor Graphics - USA)
6. The Application of Bist-Aided Scan Test for Real Chips
H. Konishi, M. Emori, T. Hiraide (Fujitsu - Japan)
7. A Scalable Architecture for On-Chip Compression: Options and Trade-Offs
A. Uzzaman, B. Keller, V. Chickermane (Cadence Design Systems - USA)
Poster Presentation
9:45-10:15
Session 5A: Panel session
10:15-11:30
Practical Needs & Wants for Silicon Debug and Diagnosis
Organizer: Fidel Muradali (National Semiconductor - USA)
Moderator: Kazuhiko Iwasaki (Tokyo Metropolitan Univ. -Japan)
Panelists:
Wu-Tung Cheng (Mentor Graphics - USA)
Mohamed Hafed (DFT Microsystems - USA)
Brion Keller (Cadence - USA)
Fidel Muradali (National Semiconductor - USA)
Tatsuo Watariumi (Sony - Japan)
Session 6A: Delay test
13:30-14:45
Chair: B. Becker (Univ. Freiburg - Germany)
6A.1 Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
X Lin, K.-H. Tsai, C. Wang, M. Kassab, J. Rajaski, T. Kobayashi, R. Klingenberg (Mentor Graphics - USA), Y. Sato, S. Hamada, T. Aikyo (STARC - Japan)
6A.2 Not all Delay Tests Are the Same - SDQL Model Shows True-Time
M. A. Uzzaman, M. Tegethoff, B. Li, K. Mccauley (Cadence Design Systems - USA), S. Hamada, Y. Sato (STARC - Japan)
6A.3 At-Speed Testing with Timing Exceptions and Constraints - Case Studies
D. Goswami, K.-H. Tsai, M. Kassab, T. Kobayashi, J. Rajaski, B. Swanson, D. Walters(Mentor Graphics - USA), Y. Sato, T. Asaka, T. Aikyo (STARC - Japan)
Session 6B: Scan test techniques (1)
13:30-14:45
Chair: C. Landrault (LIRMM, France)
6B.1 A New Scan Design Technique Based on Pre-Synthesis Thru Functions
C. Y. Ooi, H. Fujiwara (Nara Institute of Science and Technology: NAIST - Japan)
6B.2 Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage
S.-J. Wang , K.-L. Peng (National Chung-Hsing Univ. - Taiwan), K. S.-M. Li (National Sun Yat-Sen Univ. - Taiwan)
6B.3 On the Replacement of Scan Chain Inputs by Primary Input Vectors
I. Pomeranz (Purdue Univ. - USA), S. M. Reddy (Univ. of Iowa - USA)
Session 6C: Reliable circuit design
13:30-14:45
Chair: V. Agrawal (Auburn Univ., USA)
6C.1 Study of N-Detectability in QCA Designs
B. K Sikdar (Bengal Engg and Scienec Univ., - India)
6C.2 A Design of Pipelined Carry-dependent Sum Adder With its Self-checking Structure
M. Li, S. Xu, J. Cao, F. Ran, S. Ma (Shanghai Univ. - China)
6C.3 ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs
N. Karimi (University of Tehran - Iran), S. Mirkhani (University of Tehran - Iran), Z. Navabi (Northeastern Univ. - USA)
Poster presentation
14:45-15:15
Session 7A: Defect diagnosis
15:15-16:30
Chair: X. Wen (Kyushu Institute of Technology, Japan )
7A.1 Interconnect Open Defect Diagnosis with Physical Information
W. Zou (Mentor Graphics - USA), W.-T. Cheng (Mentor Graphics - USA), S. M. Reddy (Univ. of Iowa - USA)
7A.2 Defect Diagnosis - Reasoning Methodology
Y. Sato, K. Sugiura, R. Shimada, Y. Yoshizawa, K. Norimatsu (STARC - Japan), M. Sanada (Kochi Univ. of Technology - Japan )
7A.3 Diagnosis of Delay Faults due to Resistive Bridges, Delay Variations and Defects
L. Wang, S. Gupta, M. Breuer (Univ. of Southern California - USA)
Session 7B: Scan test techniques (2)
15:15-16:30
Chair: A. Uzzaman (Cadence Design Systems, USA )
7B.1 Multi-Mode segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction
P.-C. Tsai, S.-J. Wang (National Chung-Hsing Univ. - Taiwan)
7B.2 Test Data Compression Based on Clustered Random Access Scan
Y.Hu, C. Li, J. Li, Y.-H. Han, X-W. Li, W. Wang, H.-W.Li (Chinese Academy of Sciencess - China), L-T. Wang (Syn Test Technologies - USA),
X-Q. Wen (Kyushu Institute of Technology - Japan)
7B.3 Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decompostion
J. Lee, N. Touba (Univ. of Texas at Austin - USA)
Session 7C: Analog DFT
15:15-16:30
Chair: T. Yamaguchi (Advantest Laboratories Ltd., Japan)
7C.1 A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters
H. shin, J. Park, J. Abraham (Univ. of Texas at Austin - USA)
7C.2 A Digital BIST Methodology for Spread Spectrum Clock Generators
M.-H. Chou, J.-C. Hus, C. Su (National Chiao Tung Univ. - Taiwan)
7C.3 A Cost Effective Output Response Analyzer for Sigma-Delta Modulation Based BIST Systems
H.-C. Hong, S.-C. Liang (National Chiao Tung Univ. - Taiwan)
Session 8A:Defect ATPG
17:00-18:15
Chair: B. Keller (Cadence Design Systems, USA )
8A.1 Test generation for weak resistive bridges
S. Irajpour, S.Gupta, M. Breuer (Univ. of Southern California - USA)
8A.2 A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
M. Renovell (LIRMM - France), M. Comte (LIRMM - France), I. Polian (Albert-Ludwigs-Univ. of Freiburg - Germany), P. Engelke (Albert Ludwigs University - Germany), J. Becker (Univ. Karlsrvhe (th) - Germany)
8A.3 An Effective Test Pattern Generation for Signal Integrity
Y. Kim, M.-H. Yang, Y. Park, D. Y. Lee, S. Kang (Yonsei Univ. - Korea)
Session 8B: Reconfigurabilities in BIST
17:00-18:15
Chair: C.-W. Wu (National Tsing Hua Univ., Taiwan )
8B.1 A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops
X. Du (Mentor Graphics - USA), N. Mukherjee (Mentor Graphics - USA), C. J. Hill (Mentor Graphics - United Kindom), W.-T. Cheng (Mentor Graphics - USA), S. M. Reddy (Univ. of Iowa - USA)
8B.2 An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing
A. Alaghi (Univ. of Tehran - Iran), M. S. Yarandi (Univ. of Tehran - Iran), Z. Navabi (Northeastern Univ. - USA)
8B.3 Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Architecture
X. Dong (Tsinghua Univ. - China), Y. Zhao(Tsignhua Univ. - China), K. Chakrabarty (Duke Univ. - USA), J. Sun (Tsinghua Univ. - China), H. Fujiwara (Nara Institute of Science and Technology - Japan)
Session 8C: Solutions for jitter problems
17:00-18:15
Chair: J. Abraham ( Univ. Texas , USA)
8C.1 Enhanced A/D Converter Signal-to-Noise-Ratio Testing inthe Presence of Sampling Clock Jitter
S. Goyal (Georgia Institute of Teachnology - USA), A. Chatterjee (Georgia Institute of Teachnology - USA), Y. Shieh (National Semiconductor - USA)
8C.2 A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range
C.-Y. Li, C.-Y. Chou, T.-Y. Chang (National Tsing Hua Univ. - Taiwan)
8C.3 A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter
J. L. Huang (National Taiwan Univ. - Taiwan)
top
November 23
Session 9A: Test compression (1)
8:30-9:45
Chair: N. Touba (Univ. of Texas at Austin, USA)
9A.1 Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing
T. Hayashi, N. Ikeda, T. Shinogi, H. Takase, H. Kita (Mie Univ. - Japan)
9A.2 An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time
Z. Wang, K. Chakrabaty (Duke Univ. - USA)
9A.3 Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs
R. Sethuram (Rutgers Univ. - USA), S. Wang (NEC Labs - USA), S. Chakradhar (NEC Labs - USA), M. Bushnell (Rutgers Univ. - USA)
Session 9B: Diagnosis algorithms
8:30-9:45
Chair: K. Furuya (Chuo Univ., Japan )
9B.1 Fanout-based fault diagnosis for open faults on pass/fail information
K. Yamazaki (Meiji Univ. - Japan), Y. Takamatsu (Ehime Univ. -Japan)
9B.2 Diagnosis of Transistor Shorts in Logic Test Environment
Y. Higami (Ehime Univ. - Japan), K.K. Saluja (Univ. of Wisconsin - Madison - USA), H. Takahashi, S. Kobayashi, Y. Takamatsu (Ehime Univ. - Japan)
9B.3 The Next Step in Volume Scan Diagnosis: Standard Fail Data Format
A. Leininger (Infineon Technologies - Germany),
A. Khoche(Agilent Technologies - USA),
M. Fischer (Agilent Technologies - USA), N. Tamarapalli,
W.-T. Cheng, R. Klingenberg, W. Yang (Mentor Graphics - USA)
Session 9C: DFT for processors and ASICs
8:30-9:45
Chair: T. Inoue (Hiroshima City Univ. , Japan)
9C.1 DFT of the Cell Processor and its Impact on EDA Test Software
L. Bushard (IBM - USA), N. Chelstrom (Intrinsity - USA),
S. Ferguson (IBM - USA), B. Keller (Cadence Design Systems - USA)
9C.2 Design for Testability of Software-Based Self-Test for Pro cessors
M. Nakazato, S. Ohtake, M. Inoue, H. Fujiwara (Nara Institute of Science and Technology - Japan)
9C.3 Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology
B. Foutz, V. Chickermane, B. Li (Cadence Design Systems - USA), H. Linzer, G. Kunselman (IBM - USA)
Session 10A: Test compression (2)
10:15-11:30
Chair: J. Rajski (Mentor Graphics , USA)
10A.1 Interleaving of Delay Fault Test Data for Efficient Test Compression with Statistical Coding
K. Namba, H. Ito (Chiba Univ. - Japan)
10A.2 BCH-based Compactors of Test Responses with Controllable Masks
T. Reungpeer (Santa Clara Univ. - USA), X. Qian (Santa Clara Univ. /Intel - USA ), S. Mourad (Santa Clara Univ. - USA)
10A.3 Expansion of Convolutional Compactors over Galois Field
M. Arai, S. Fukumoto, K. Iwasaki (Tokyo Metropolitan Univ. - Japan)
Session 10B: Diagnosis techniques
10:15-11:30
Chair: K. Chakrabarty (Duke Univ., USA )
10B.1 Diagnosing At-speed Scan BIST Circuits Using a Low Speed and Low Memory Tester
Y. Nakamura (NEC Electronics - Japan), T. Clouqueur (Nara Institute of Science and Technology - Japan), K. K. Saluja (Univ. of Wisconsin - Madison - USA) , H. Fujiwara (Nara Institute of Science and Technology - Japan)
10B.2 Early Life Cycle Yield Learning for Nanometer Devices Us
ing Volume Yield Diagnostics Analysis
S. Seike, K. Namura, Y. Ohya (IBM Industrial solution - Japan), M. A. Uzzaman, S. Arima, D. Meehi, V. chickermane (Cadence Design Systems - USA), A. Kobayasi, S. Tanaka, H. Adachi (Renesas Technology - Japan)
10B.3 Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor
S. Wichlund, E. J. Aas (Nordic Semiconductor ASA - Norway)
Session 10C: Network issues
10:15-11:30
Chair: X. Li (Chinese Academy of Science, China)
10C.1 Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking
C. Liu (Univ. Nebraska - USA)
10C.2 An External Test Approach for Network-on-a-Chip Switches
J. Raik, V. Govind, R. Ubar (Tallinn Technological Univ. - Estonia)
10C.3 Plug once, test everything. Configuration management in IPv6 Interop Testing
A. Sabiguero, C. Viho (IRISA - Uruguay )
-----------------------------------------------------------------------------------------------------------------------------------------------
------------------------------