10th Workshop on RTL and High Level Testing, WRTLT'09



The Ninth IEEE Workshop on RTL and High Level Testing
November 27-28,
The Chinese University of Hong Kong,
Hong Kong SAR, China

Sponsored by
IEEE Computer Society Test Technology Technical Council
IEICE-ICS, Technical Committee on Dependable Computing

Supported by
Institute of Computing Technology, CAS
The Chinese University of Hong Kong

The purpose of this workshop is to bring researchers and practitioners on LSI testing from all over the world together to exchange ideas and experiences on register transfer level (RTL) and high level testing. WRTLT'09, the tenth workshop, will be held in Hong Kong SAR, China. We expect this workshop to provide an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.

Areas of interest include but are not limited to:
- Functional fault modeling - RTL ATPG
- Microprocessor testing - RTL BIST
- Relationship between RTL
and gate level testing - Design verification
- High level test bench generation - SoC testing
- High level approaches for testing - RTL DFT

Authors are invited to submit paper proposals for presentation at the workshop. The proposal may be an extended summary (1,000 words) or a full paper and should include: title, full name and affiliation of all authors, 50 words abstract, keywords and the name of contact author. All submissions should be sent to the following address as Postscript or PDF attachment.

Paper submission by E-mail:wrtlt09@cse.cuhk.edu.hk

The submission will be considered evidence that upon acceptance the author(s) will prepare the final manuscript in time for inclusion in the digests and will present the paper at the Workshop.

Key Dates
Submission deadline: August 4, 2009
Notification of acceptance: September 11, 2009
Camera-ready copy: October 10, 2009
Workshop: November 27-28, 2009
General Chair
Krishnendu Chakrabarty
Duke University
Program Co-Chair(s)
Qiang Xu
The Chinese University of Hong Kong
Yinhe Han
Institute of Computing Technology, CAS
Panel Chair
Yu Huang
Mentor Graphics
Publicity Chair
Lei Zhang
Institute of Computing Technology, CAS
Publication Chair
Wei Wang
HeFei University of Technology, China
Finance Chair
Yubin Zhang
The Chinese University of Hong Kong
Registration Chair
Xiao Liu
The Chinese University of Hong Kong
Local Arrangement Chair
Feng Yuan
The Chinese University of Hong Kong
Ex Officio
Kazumi Hatayama
STARC, Japan
Steering Committee
Chair: Xiaowei Li, China
Vice-Chair: Tomoo Inoue, Japan
Hideo Fujiwara, Japan
Terumine Hayashi, Japan
Kazuhiko Iwasaki, Japan
Erik Larsson, Sweden
Alex Orailoglu, USA
Kewal K. Saluja, USA

Program Committee
Bhargab Bhattacharya
Jinian Bian
Masaki Hashizume
Terumine Hayashi
Toshinori Hosokawa
Yu Hu
Yu Huang
Michiko Inoue
Tomoo Inoue
Seiji Kajihara
Erik Larsson
Chien-Mo Li
Huawei Li
Huaguo Liang
Jing-Jia Liou
Srinivas Patil
Tsuyoshi Shinogi
Virendra Singh
Mohammad Tehranipoor
Baosheng Wang
Xiaoqing Wen
Dong Xiang
Tomokazu Yoneda
Zhiqiang You
Danella Zhao

WRTLT'09 Advance Program
November 27--28, 2009

November 27 (Friday)

Registration 8:00 -- 8:40 .
Opening session 8:40 -- 9:00
Keynote speech 9:00 -- 10:00

System-Level Verification and Test: From Microprocessors to SoCs and Multicore Chips

Jacob Abraham (UT Austin -- USA)
Coffee break 10:00 -- 10:30
Session 1 RTL and High-Level Testing 10:30 -- 11:50
   Chair: Tomoo Inoue (Hiroshima City University -- Japan)
A DFT Method for Functional Scan at RTL

Marie Engelene, J. Obien and Hideo Fujiwara ( Nara Institute of Science and Technology -- Japan)
Observation-Point Selection at Register-Transfer Level to Increase Defect Coverage for Functional Test Sequences

Hongxia Fang 1, Krishnendu Chakrabarty 1 and Hideo Fujiwara 2 ( 1 Duke University - USA, 2 Nara Institute of Science and Technology -- Japan)
A Study of Software-Level Delay Fault Simulation for JPEG Decoder Application on CMP

Shun-Yen Lu, Tso-Hua Chien and Jing-Jia Liou ( National Tsing Hua University -- Taiwan)
Path-Based Resource Binding to Reduce Delay Fault Test Cost

Michiko Inoue, Satoshi Ohtake, Yu-ichi Uemoto, and Hideo Fujiwara ( Nara Institute of Science and Technology -- Japan)

Lunch & Poster 12:00 -- 13:30

Invited talk 13:30 -- 14:15

A research perspective on post-silicon validation and debug

Nicola Nicolici (McMaster Univ. -- Canada)
Session 2 Low-Power Testing 14:20 -- 15:20     
Chair: Xiaoqing Wen (Kyushu Institute of Technology -- Japan)
Low Capture Power Adjacent Fill (LCPAF) in Test Data Compression Environment

Jia Li 1, Qiang Xu 2 and Dong Xiang 1 (1 Tsinghua University - China, 2 The Chinese University of Hong Kong - Hong Kong)
Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC

Jaynarayan T Tudu 1, Erik Larsson 2, Virendra Singh 1, and Hideo Fujiwara 3 (1. Indian Institute of Science -India, 2. Linkoping University - Sweden, 3. Nara Institute of Science and Technology -- Japan)
Efficient Modeling of IR-Drop Using Dynamic SDF for Test and Diagnosis

Ke Peng 1, Yu Huang 2, Wu-Tung Cheng 2, and Mohammad Tehranipoor 1 (1 University of Connecticut -- USA, 2 Mentor Graphics -- USA)
Coffee break 15:20 -- 15:40
Session 3 Fault Simulation and Test Generation 15:40 -- 17:00 
Chair: Jing-Jia Liou ( National Tsing Hua University -- Taiwan)    
A Fast and Memory-Efficient Fault Simulation Using GPU

Dawen Xu, Yinhe Han, Huawei Li, and Xiaowei Li ( Chinese Academy of Sciences -- China)
3.2 Test Generation for Open Faults Considering the Effects of Adjacent Lines

Ryota Kuribayashi, Hiroyuki Yotsuyanagi, and Masaki Hashizume ( The Univ. of Tokushima -- Japan)
Compact Test Generation for Complete Coverage of Path Delay Faults in a Standard Scanned Circuit

Dong Xiang and Zhen Chen ( Tsinghua University - China)
X-Identification According to Required Distribution for Industrial Circuits

Isao Beppu, Kohei Miyase, Yuta Yamato, Xiaoqing Wen,and Seiji Kajihara (Kyushu Institute of Technology -- Japan)
Panel 17:00 -- 18:30

Test / Diagnosis at Multi-Core / Multi-Die Era

Organizer and Moderator: Yu Huang (Mentor Graphics -- USA)

Kazumi Hatayama (STARC -- Japan)

Zebo Peng (Linkoping University -- Sweden)

Yasuo Sato (Kyushu Institute of Technology -- Japan)

James Chien-Mo Li (National Taiwan University -- Taiwan)

Ilia Polian (Albert Ludwigs University of Freiburg -- Germany)

Social Event 18:30 -- 22:30

November 28 (Saturday)

Invited talk 8:30 -- 9:15

Quality, Cost and Time-to-Market: We Need Them All

Xinli Gu (Cisco -- USA)
Session 4 Design for Testability 9:20 -- 11:00
Chair: Ilia Polian (Albert Ludwigs Univ. of Freiburg -- Germany)
Is the Full Scan Design Unshakeable?

Yinhua Min (Chinese Academy of Sciences -- China)
A Design of Concurrently Testable Response Analyzers in Built-in Self-Test

Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara,and Tomoo Inoue (Hiroshima City University -- Japan)
A Low Cost Self-Hold Analog Test Wrapper Design for Mixed-Signal SOCs

Yang Jin, Hong Wang, and Shiyuan Yang (Tsinghua University - China)
Improving Transition Delay Fault Coverage with Partial Enhanced Scan Technique

Songwei Pei, Huawei Li, and Xiaowei Li (Chinese Academy of Sciences -- China)
Scan Slice Compression Technique Using Dynamical Updating Reference Slices

Jun Liu, Yinhe Han, and Xiaowei Li (Chinese Academy of Sciences -- China)
Coffee break 11:00 -- 11:20
Session 5 Diagnosis and Fault-Tolerance 11:20 -- 12:40
Chair: Huawei Li (Chinese Academy of Sciences -- China)
Diagnosis of Logic-chain Bridging Faults

#Wei-Chih Liu, Wei-Lin Tsai, Hsiu-Ting Lin,and James Chien-Mo Li (National Taiwan University -- Taiwan)
An Even-Odd DFD Technique for Scan Chain Diagnosis

Venkat Rajesh A 1, Erik Larsson 2,Virendra Singh 3, and MS Gaur 1 (1 Indian Institute of science - India, 2 Linkoping University - Sweden, 3 Malaviya National Instituet of Technology -- India)
Transition Fault Diagnosis Using At-speed Test Patterns

Shang-Feng Chao, Jheng-Yang Ciou, and James Chien-Mo Li (National Taiwan University -- Taiwan)
On Predicting the Maximum Circuit Aging

Song Jin, Yinhe Han, Huawei Li, and Xiaowei Li (Chinese Academy of Sciences -- China)

The Impact of Performance Asymmetry on Topology Reconfiguration in NoC-based Many-core Systems

Yue Yu 1, Lei Zhang 1, Jianbo Dong 1, Yinhe Han 1, and Shangpin Ren 2 (1 Chinese Academy of Sciences - China, 2 Illinois Institute of Technology -- USA)
A Thermal-aware Parallel Multicast Testing Method Based on Many-core Chips

Fang Fang 1, Wei Wang 1, Yinhe Han 2, and Xiaowei Li 2 (1 Hefei University of Technology - China, 2 Chinese Academy of Sciences - China)
A Particle Swarm Optimization-based BPNN Approach for Fault Diagnosis of Analog Electronic Circuits

Wenji Zhu and Yigang He (Hunan University -- China)
Microprocessor Modeling for Board Level Test Access Automation

Sergei Devadze 1, Artur Jutman 1, Anton Tsertov 2, and Raimund Ubar 2 (1 Testonica Lab Ou¨ - Estonia, 2 Tallinn Univ. of Technology -- Estonia)
Hierarchical Formal Verification Method based on Transactions

Zhiqiu Kong, Jinian Bian, Yanni Zhao, and Shujun Deng (Tsinghua University - China)
Semi-Confliction Guided Problem Partitioning Algorithm in FPGA-based SAT Solver

Zhongda Yuan and Jinian Bian (Tsinghua University - China)
A Low Power Test Scheme Based on Segment Fixing Folding Counter

Tian Chen, Hua-guo Liang, Min-sheng Zhang, Wei Wang, and Mao-xiang Yi (Hefei University of Technology - China)
SORPECO: Localized SOR Analysis Method for Power/Ground Networks in ECO Placements

Zuying Luo 1, Guoxing Zhao 1, and Jinhe Zhou 2 (1 Beijing Normal University - China, 2. Beijing Information Science and Technology University -- China)
Modeling Test Flows of Automated Test Equipment Test Program Using Simple Graph

Hui Jia Tai 1, Chin Kuan Ho 1, Hze Horng Ong 2, Somnuk Phon-Amnuaisuk 1, Siew Beng Thum 2 (1 Multimedia University - Malaysia, 2 Intel Corporation, -- Malaysia)
A Model for Scan Insertion at the Register Transfer Level

Lilia Zaourar 1, Yann Kieffer 1, Chouki Aktouf 2, Vincent Juliard 2
(1 G-SCOP laboratory - France, 2 DeFacTo Technologies -- France)