1st Workshop on RTL ATPG & DFT

 
Workshop on RTL ATPG & DFT (WRTLT'00)

Changsha, Hunan, China, Sept. 26-27, 2000

Sponsored by
IEEE COMPUTER SOCIETY TEST TECHNOLOGY TECHNICAL COUNCIL


In cooperation with
Technical Committee on Fault-Tolerant Computing, China Computer Federation
National Natural Science Foundation of China

Hosted by
Hunan University


CALL FOR PRESENTATION

Register Transfer Level (RTL) Automatic Test Pattern Generation (ATPG) and Design For Testability (DFT) are considered to be very important recently for deep-submicron IC technology, while gate level ATPG & DFT are challenging. The workshop on RTL ATPG & DFT provides a forum for specialists to discuss issues. The workshop will put the emphasis on interchanging ideas and implementation experiences. No proceedings will be published. Original papers to be published elsewhere very soon can be presented in this workshop in detail. Collection of presentation outlines or full papers will be informally printed and distributed for audience. Software demonstrations are especially welcome. Each presentation will give 40 minutes with demonstrations and 20 minutes discussions for sufficient interaction.

The workshop will be held in the campus of Hunan University, which stands at the foot of the evergreen Yuelu Mountain with the Xiang River flowing in the east. Hunan University traces its origin to Yuelu Academy in Song Dynasty in 976 A.D. more than one thousand years ago.

Topics of interests include (but not limited to):
Functional fault modeling
RTL ATPG
RTL DFT
Relationship between RTL and gate level testing

Submit your extended summary or a full paper to
Prof. Da Fang Zhang, Program Chair
Department of Computer Science,
Hunan University,
Changsha, Hunan, China, 410082
Tel: 086-731-8821702
FAX: 086-731-8822417
E-mail: wrtlt2000(at)mail1.hunu.edu.cn

Electronic submissions (in .ps or .PDF format) are preferred.
Submissions should include a topic, affiliation and address of each author, and the contact author with post and e-mail address.

Submission deadline: June 30, 2000
Acceptance notification: July 31,2000.

Co-chairs: Yinghua Min, Institute of Computing Technology, CAS, China
e-mail: min(at)mimi.cnc.ac.cn
Hideo Fujiwara, Nara Institute of Science and Technology, Japan
e-mail: fujiwara(at)is.naist.jp
Program Chair: Da Fang Zhang, Hunan University, China
e-mail: dfzhang(at)mail.hunu.edu.cn
Program Committee:: ( to be determined)

More information is available from http://cs.hunu.edu.cn/wrtlt , or contact dfzhang(at)mail.hunu.edu.cn .

--------------------- Advance Program --------------------------------------------------------
Workshop on RTL ATPG & DFT
(WRTLT00)
Changsha, Hunan, China
Sept. 26-27,2000

Sponsored by
IEEE COMPUTER SOCIETY TEST TECHNOLOGY TECHNICAL COUNCIL
In cooperation with
National Natural Science Foundation of China
Technical Committee on Fault-Tolerant Computing, China Computer Federation
Hosted by
Hunan University

Workshop Web Page: http://cs.hunu.edu.cn/wrtlt, http://wrtlt.home.chinaren.com

Advance Program
Monday, September 25, Dolton Hotel
Registration: Dolton Hotel, 8:00-21:00
Reception: Dolton Hotel, 19:00-21:00

Tuesday, September 26, Hunan University
Session 1: Opening session 9:00-11:00, at Yuelu Academy, Hunan University.
Chair and Moderator: Yinghua Min, Institute of Computing Technology, CAS, China
Keynote: “Design for Testability for Core-Based System-on-Chip”
H. Fujiwara, Nara Institute of Science and Technology, Japan
Inside tour: 11:00-12:00 at Yuelu Academy
Lunch: 12:00, Hunan University
Session 2: Test Generation (1), 13:30-15:00
Chair: Hideo Tamamoto, Akita University, Japan
2-1 “Test Generation and Design-for Testability Based on Acyclic Structure with Hold Registers”
T. Inoue, et al., Hiroshima City University, Japan
2-2 “An Efficient Method for Behavioral RTL ATPG”
Zhigang Yin, et al., Institute of Computing Technology, CAS, China
2-3 “A Parallel ATPG Algorithm Based on Big Functional Block Partitioning”
Zhide Zeng, National University of Defense Technology, Changsha, China
Break: 15:00-15:30
Session 3: Scan Design (1), 15:30-17:00
Chair: Shiyi Xu, Shanghai University, China
3-1 “RTL Partial Scan Design System: REPS”
T. Hosokawa, et al., Matsushita Electric Industrial Co., Ltd., Japan
3-2 “A Built-In Test Scheme for Pipelined Multipliers and Dividers”
Hao-Yung Lo, et al., Feng Chia University, Tsing Hua University, Taiwan
Tour and Dinner: 17:00-20:00 Yuelu Mountain

Wednesday, September 27, Dolton Hotel
Session 4: Design for Testability (1), 8:30-10:00
Chair: Zhongcheng Li, Institute of Computing Technology, CAS, China
4-1 “A DFT Method for Single-Control Testability of RTL Data Paths for BIST”
T.Masuzawa, et al., Nara Institute of Science and Technology, Japan
4-2 “A Non-Scan DFT Method at RTL Based on Fixed-Control Testability to Achieve 100% Fault
Efficiency”
S. Ohtake, et al., Nara Institute of Science and Technology, Japan
Coffee break: 10:00-10:30
Session 5: Scan Design (2), 10:30-12:00
Chair: Xiaowei Li, Peking University, China
5-1 “RTL Scan Design”
Weikang Huang, Fudan University, Shanghai, China
5-2 “A Non-Scan Testable Design of Sequential Circuits by Improving Controllability”
Hideo Tamamoto, et al, Akita University, Japan
5-3 “Verifying Stacks and Queues using Symbolic Simulation Techniques”
Y. Morihiro, et al., Tokyo Institute of Technology, Tokyo, Japan
Session 6: Test Generation (2), 13:30-15:00
Chair: K.Hatayama, Hitachi, Ltd., Japan
6-1 “A Forecasting and Evaluation System for Test Generation Algorithms”
Shiyi Xu, Shanghai University, Shanghai, China
6-2 “Target-Fault-Oriented Test Generation of Sequential Circuits Using Genetic Algorithm”
Li Shen, Institute of Computing Technology, CAS, Beijing, China
6-3 “A Structure-Oriented RTL ATPG”
Xiaolu Huang et al., Hunan University, Changsha, China
Coffee break : 15:00-15:30
Session 7: Design for Testability (2), 15:30-17:00
Chair: T. Inoue, Hiroshima City University, Japan
7-1 “Adding Transitions of Undefined States to State Transition Tables for Testability
Enhancement”
H. Yotsuyangagi, et al., The University of Tokushima, Japan
7-2 “IC Testing by Phase Classification Based on Behavioral Description of RTL”
Huawei Li, et al., Institute of Computing Technology, CAS, Beijing, China
Banquet and Entertainment: 19:00-21:00

WRTLT00 Organization
Co-chairs
Yinghua Min, Institute of Computing Technology, CAS, China, min(at)mimi.cnc.ac.cn
Hideo Fujiwara, Nara Institute of Science and Technology, Japan, fujiwara(at)is.naist.jp
Program Chair
Dafang Zhang, Hunan University, China, dfzhang(at)fm365.com , dfzhang(at)mail.hunu.edu.cn
Finance Chair
Jishun Kuang, Hunan University, China, kjsh(at)mail.hunu.edu.cn
Local Arrangements Chair
Zhuolei Cheng, Hunan University, czlzui(at)fm365.com

Program Committee
Kazumi Hatayama, Hitachi, Ltd, Japan
Terumine Hayashi, Mie University, Japan
Yigang He, Hunan University, China
Toshinori Hosokawa, Matsushita Electric, Japan
Weikang Huang, Fudan University, China
Tomoo Inoue, Hiroshima City University, Japan
Jishun Kuang, Hunan University, China
Zhongcheng Li, Institute of Computing Technology, CAS, China
Xiaowei Li, Peking University, Beijing, China
Toshimitsu Masuzawa, NAIST, Japan
Kewal K. Saluja, University of Wisconsin, USA
Yichuang Sun, Hertfordshire University, UK
Hideo Tamamoto, Akita University, Japan
J.Paulo Teixeira, IST/INESC, Portugal
Xiaoqing Wen, SynTest Technologies, Inc. USA
Hans-Joachim Wunderlich, Universitaet Stutigart, Germany
Shiyi Xu, Shanghai University, China
Zhide Zeng, National University of Defense Technology, China

Social Activities
Monday, September 25
Reception: Dolton Hotel, 19:00-21:00

Tuesday, September 26
Inside tour: Yuelu Academy, 11:00-12:00
Tour and Dinner: Yuelu Mountain, 17:00-20:00

Wednesday, September 27
Banquet and Entertainment: Dolton Hotel, 19:00-22:00

Thursday, September 28--30
Tour to Zhang Jiajie:
Zhang Jiajie is the best national forest Park in China with big wonderful mountains. The tour takes three days, Sept.28-Sept.30. We take train from Changsha 7:58, and arrive Zhang Jiajie 12:48 until Sept. 30 Noon. People can leave there for Beijing, Guangzhou, or Changsha by air in the afternoon, Sept.30. We live in five/three star hotels.

Tour Fees
The tour fees include transportation, tickets, meals and hotel. The total cost is US$200. For accompany persons without an additional hotel room, the additional cost is US$80.

Registration Fees
The registration fees include admission to all technical sessions, one lunch, coffee breaks, reception, banquet, and a copy of the digest of papers of the workshop.
Status By Aug. 30 After Aug. 30
ACM/IEEE Member $160 $190
Non Members $200 $240
Full time Students $100 $120

Hotel reservation
Dolton Hotel *
Name Fax
Organization
E-mail Address
Arrival Date Time Departure Date Time
Share Room with
Superior Room (2 Queen beds) US$75
Deluxe Room (1 King bed) US$90/night
* Dolton Hotel(通程国际大酒店) is a five star hotel.

Payment Information
If we receive your return receipt before Aug.30, we regard as you have pre-registration, the hotel and tour are reserved. You have to pay US dollars by cash or traveler's check at the registration desk. Please copy the forms, and return to WRTLT2000, Dept. of Computer, Hunan University, Changsha, China, 410082 before Aug. 30.
Registration (US$)
Hotel Reservation (US$)
Tour Reservation (US$)
Total (US$)
I will pay the total at the registration desk.
Signature

Contact
For more information please visit our Web site: http://wrtlt.home.chinaren.com,
http://cs.hunu.edu.cn/wrtlt, or email to czlzui(at)fm365.com, wrtlt2000(at)mail1.hunu.edu.cn