2nd Workshop on RTL ATPG & DFT, WRTLT'01



Workshop on RTL ATPG & DFT
Nara-Machi Center, Nara, Japan
November 22-23, 2001


Sponsored by
IEEE Computer Society Test Technology Technical Council
In Corporation with
Technical Group on Fault Tolerant Systems, IEICE


The Workshop on RTL ATPG & DFT (WRTLT) provides an
international forum for interchanging ideas and
implementation experiences on register transfer (RT)
level automatic test pattern generation (ATPG) and design
for testability (DFT). For systems on chip (SOC) devices,
it has become a real hot topic to improve VLSI
testability using high-level descriptions. Now in its
2nd year, just after the ATS'01, papers are solicited on
all aspects of RT-level testing techniques. Photocopies
of accepted papers will be handed out at the workshop
site. We hope and expect the workshop will provide all
participants with new ideas and food for thought through
informal interactions and discussions.

Topics of interests include (but not limited to):
Functional fault modeling
RT-level ATPG
RT-level DFT
RT-level BIST
Relationship between RT-level and gate-level testing

Submission : July 31, 2001
Acceptance : August 31, 2001
Final version : to be announced

- Submissions must be made as Postscript or PDF attachments to
e-mail sent to wrtlt(at)info.eei.metro-u.ac.jp
- Submissions must be a complete paper of 10 pages maximum, or
an extended summary from four to six pages
- The title page must include abstract, keywords, full mailing address,
telephone and Fax number and e-mail address
- An author of every accepted paper must present at the workshop

For up-to-date information refer to the WRTLT'01 website
or contact the workshop chairs.

Nara is an ancient capital of Japan. In the end of
November, you can enjoy not only a beautiful combination
of red and yellow autumnal leaves but also historical
shrines and temples. For more on tourism, a couple of
links will be found at the above site.

General Chair:
Hideo Tamamoto, Akita University, Japan
Program Co-Chairs:
Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan
Xiaowei Li, Peking University, China
Financial Chair:
Hiroshi Yokoyama, Akita University, Japan
Local Arrangements Chair:
Michiko Inoue, NAIST, Japan

Program Committee Members:
Satoshi Fukumoto, Tokyo Metropolitan University, Japan
Sandeep K. Gupta, University of Southern California, USA
Kazumi Hatayama, Hitachi, Ltd., Japan
Terumine Hayashi, Mie University, Japan
Toshinori Hosokawa, STARC, Japan
Weikang Huang, Fudan University, China
Tomoo Inoue, Hiroshima City University, Japan
Zhongcheng Li, ICT, Chinese Academy of Sciences, China
Toshimitsu Masuzawa, Osaka University, Japan
Kewal K. Saluja, University of Wisconsin-Madison, USA
Yihe Sun, Tsinghua University, China
J. Paulo Teixeira, IST/INESC, Portugal
Xiaoqing Wen, Syntest Tech., USA
Cheng-Wen Wu, Tsing Hua University, Taiwan
Shiyi Xu, Shanghai University, China
Hee Yong Youn, SungKyunKwan University, Korea
Dafang Zhang, Hunan University, China

WRTLT Steering Committee
Chair: Yinghua Min, Academia Sinica, China
Hideo Fujiwara, NAIST, Japan
Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan
Xiaowei Li, Peking University, China
Kewal K. Saluja, University of Wisconsin, USA
Hideo Tamamoto, Akita University, Japan
J. Paulo Teixeira, IST/INESC, Portugal
Dafang Zhang, Hunan University, China

WRTLT'01 Final Program

Registration (Meeting room 4, Naramachi center 3F)
19:00 - 21:00 Nov. 21
8:40 - 18:00 Nov. 22
9:00 - 15:00 Nov.23

Technical Session (Meeting room 2, Naramachi center 3F)

Nov. 21, 2001

19:00 - 21:00 (Kissa Naramachi, Naramachi center 1F)

Nov. 22, 2001

9:00 - 9:15

Invited talk
9:15 - 10:00 (45-min)
Chair : K. Iwasaki
VCore Based Design Technology for the Next Generation SOC
M. Muraoka - Semiconductor Technology Academic Research Center, Japan

Session 1
10:20 - 12:00 (100-min)
Chair : K. Hatayama

1.1 : Why RTL ATPG?
Y. Min - Chinese Academy of Sciences, China
1.2 : A Scheduling Method in High-Level Synthesis for RTL Acyclic Partial Scan Design
T. Inoue, T. Miura, A. Tamura - Hiroshima City University, Japan
H. Fujiwara - Nara Institute of Science and Technology, Japan
1.3 : Modeling and Organizing of RTL Transfer Faults
Z. Yin, Y. Min, X. Li - Chinese Academy of Sciences, China
1.4 : Partial Scan Testing on the Register-Transfer Level
B. S. Greene - C-Level Design Inc., U.S.A.
S. Mourad - Santa Clara University, U.S.A.

Steering Committee Meeting (members only)
(Meeting room 1, Naramachi center3F)
12:00 - 13:30

Session 2
13:30 - 14:45 (75-min)
Chair : T. Masuzawa

2.1 : Design for Consecutive Testability of Systems-on-a-Chip with Built-In Self Testable Cores
T. Yoneda, H. Fujiwara - Nara Institute of Science and Technology, Japan
2.2 : Memory-Based Reconfigurable Chip Architecture and Its RT-Level BIST
Y. Yamada, Y. Ichinoseki, K. Ichino, S. Fukumoto, K. Iwasaki - Tokyo Metropolitan University, Japan
M. Sato - Hitachi, Ltd., Japan
2.3 : Circular ScanBIST: A Highly Efficient BIST Technique for Sequential Circuits
K. S. Kim - Intel Corporation, U.S.A.

Session 3
15:00 - 16:15 (75-min)
Chair : S. Fukumoto

3.1 : Devising an RT-Level ATPG for uProcessor Cores
F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero - Politecnico di Torino, Italy
3.2 : Constraint Driven Pin Mapping for Concurrent SOC Testing
Y. Huang, S. M. Reddy - University of Iowa, U.S.A.
N. Mukherjee, C. Tsai, O. Samman, Y. Zaidan, Y. Zhang, W. Cheng - Mentor Graphics Corporation, U.S.A.
3.3 : A DSP-based Test Scheme and Its Optimization for Systems on a Chip
H. Hu, S. Yihe - Tsinghua University, China

Session 4
16:30 - 18:00 (90-min)
Chair : K. Saluja

4.1 : Semi-Random Testing for Combinational Circuits
S. Xu, J. Chen - Shanghai University, China
4.2 : Module-based Hierarchical Test Generation for Combinational Circuits at Register-Transfer Level
X. Huang, D. Zhang, Y. Min - Human University, China
4.3 : A flexible platform for the functional validation of programmable circuits
R. Velazco, F. Faure - TIMA Laboratory, France
4.4 : Non-Scan Design for Testability for RTL Circuits Based on Conflict Analysis
D. Xiang, S. Gu - Tsinghua University, China
4.5 : An FSM-Based Programmable Memory BIST Architecture
P.-C. Tsai, S.-J. Wang - National Chung-Hsing University, Taiwan, ROC
4.6 : A Non Scan DFT Method using Functional Information of Operational Modules
H. Date, T. Hosokawa, M. Muraoka - Semiconductor Technology Academic Research Center, Japan

Banquet (Garden room, Hotel Fujita 1F)
18:30 - 20:30

Nov. 23, 2001

Session 5
9:00 - 10:15 (75-min)
Chair : Z. Li

5.1 : High-Level Analysis for Effective Test
J. A. Abraham - The University of Texas at Austin, U.S.A.
5.2 : Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
Y. Makris - Yale University, U.S.A.
A. Orailoglu - U. C. San Diego, U.S.A.
5.3 : A design for hierarchical testability for RTL data paths using extended data flow graphs
S. Nagai, S. Ohtake, H. Fujiwara - Nara Institute of Science and Technology, Japan

Session 6
10:40 - 11:30 (60-min)
Chair : H. Li
6.1 : Low Power Test Compatibility Classes: Exploiting regularity for simultaneous reduction in test application time and power dissipation
N. Nicolici - McMaster University, Canada
B. M. Al-Hashimi - University of Southampton, U.K.
6.2 : Test Power Reduction for Full Scan Sequential Circuits by Test Vector Modification
S. Kajihara, K. Ishida, K. Miyase - Kyushu Institute of Technology, Japan

11:30 - 13:00

Session 7
13:00 - 14:40 (100-min)
Chair : S. Xu

7.1 : Path Delay Test Generation for Standard Scan Designs Using State Tuples
Y. Shao, S. M. Reddy - University of Iowa, U.S.A.
I. Pomeranz - Purdue University, U.S.A.
7.2 : Compact TPG Design for a Deterministic BIST Scheme
T. Hayashi, T. Suzuki, T. Shinogi, H. Kita, H. Takase - Mie University, Japan
7.3 : Efficient RT-level Test Generation Techniques based on Refinement of Finite-state Machines
H. Li, Y. Min - Chinese Academy of Sciences, China
7.4 : A Compacted Test Plan Table Generation Method for RTL Data Path Circuits
T. Hosokawa, H. Date, M. Muraoka - Semiconductor Technology Academic Research Center, Japan

14:40 -
Todaiji Temple tour (the Great Buddha etc.)