9th Workshop on RTL and High Level Testing, WRTLT'08

[http://aries3a.cse.kyutech.ac.jp/wrtlt08/]
________________________________________

CALL FOR PAPERS
The Ninth IEEE Workshop on RTL and High Level Testing
Nov. 27-28, 2008 ACU (Advanced Center for Universities), Sapporo, Japan

Sponsored by
IEEE Computer Society Test Technology Technical Council
Technical Group on Dependable Computing, IEICE

Scope
The purpose of this workshop is to bring researchers and practitioners on LSI testing from
all over the world together to exchange ideas and experiences on register transfer level
(RTL) and high level testing. WRTLT'08, the ninth workshop, will be held in conjunction
with the 17th Asian Test Symposium (ATS'08) in Sapporo, Japan. Areas of interest include
but are not limited to:
(1) High level testing -- RTL/Behavior level testing, High level approaches for testing,
RTL ATPG, RTL DFT, RTL BIST, Synthesis for testability, Relationship between RTL
and gate level testing, Functional fault modeling, High level test bench generation
(2) SoC testing -- Test scheduling, Core testing, Interconnect testing, NoC testing
(3) Reliable SoC -- System level reliability, Self repair, Fault tolerant SoC
(4) Micro processor testing
(5) Design Verification
(6) Gate level test related issues -- Low power testing, Test compression, ATPG, DFT,
BIST
This year we will set up the theme of "Power/Thermal-Aware Testing", which we believe
needs to be discussed not only at gate level but also from high level in this workshop.
Paper submissions related to this theme are especially welcomed. Panel discussion and a
special session on this theme are being planned.
We hope and expect this workshop provides an ideal forum for frank discussion on this
important topic for the future system-on-a-chip (SoC) devices.

Submissions
Authors are invited to submit paper proposals for presentation at the workshop. The
proposal may be an extended summary (1,000 words) or a full paper and should include:
title, full name and affiliation of all authors, 50 words abstract, keywords and the name of
contact author. All submissions should be sent to the following address as Postscript or
PDF attachment.
wrtlt08submission@ip.elec.mie-u.ac.jp
The submission will be considered evidence that upon acceptance the author(s) will
prepare the final manuscript in time for inclusion in the digests and will present the paper
at the Workshop.

Key Dates
Submission deadline: August 4, 2008
Notification of acceptance: September 11, 2008
___________________________________________________________________________________________________________
General Chair
Tomoo Inoue
Hiroshima City University
General Vice-Chair
Toshinori Hosokawa
Nihon University
Program Chair
Tsuyoshi Shinogi
Mie University
Finance Chair
Satoshi Ohtake
NAIST
Publicity Chair
Xiaoqing Wen
Kyushu Institute of Technology
Publication Chair
Tomokazu Yoneda
NAIST
Registration Chair
Hiroyuki Yotsuyanagi
Tokushima University
Local Arrangement Chair
Hiroshi Yokoyama
Akita University
Audio Visual Chair
Masayuki Arai
Tokyo Metropolitan University
Secretary
Hideyuki Ichihara
Hiroshima City University
Ex Officio
Hideo Fujiwara
NAIST
Further Information
Email:
wrtlt08@aries30.cse.kyutech.ac.jp
http://aries3a.cse.kyutech.ac.jp/wrtlt08

Program Committee
Takashi Aikyo, Japan
JiNian Bian, China
Krishnendu Chakrabarty, USA
Tsin-Yuan Chang, Taiwan
Satoshi Fukumoto, Japan
Masaki Hashizume, Japan
Kazumi Hatayama, Japan
Terumine Hayashi, Japan
Yu Hu, China
WRTLT’08
Michiko Inoue, Japan
Hideo Ito, Japan
Kazuhiko Iwasaki, Japan
Seiji Kajihara, Japan
Erik Larsson, Sweden
Hua-Wei Li, China
Xiao-Wei Li, China
Zainalabedin Navabi, USA
Chia Yee Ooi, Malaysia
Alex Orailoglu, USA
Ilia Polian, Germany
Jaan Raik, Estonia
Kewal K. Saluja, USA
Hideo Tamamoto, Japan
Dong Xiang, China
ZhiQiang You, China
Danella Zhao, USA
Steering Committee
Chair: Xiaowei Li, China
Vice-Chair: Tomoo Inoue, Japan
Members:
Hideo Fujiwara, Japan
Terumine Hayashi, Japan
Kazuhiko Iwasaki, Japan
Erik Larsson, Sweden
Alex Orailoglu, USA
Kewal K. Saluja, USA
Hideo Tamamoto, Japan
Dong Xiang, China
Dafang Zhang, China
___________________________________________________________________________________________________________

version 3, Nov 4
WRTLT'08 Advance Program
November 27--28, 2008

Room K in ACU (Advanced Center for Universities)
Nihon Seimei Sapporo Building 5th floor
Kita-3Jo Nishi-4Chome 1, Chuo-ku, Sapporo, Japan


November 27 (Thursday)


Registration 11:30 -- Room K in ACU
Welcome lunch 12:30 -- 13:30 Room K in ACU


Opening session 13:30 -- 13:50
Keynote speech 13:50 -- 14:25

Power-Aware System-on-Chip Test Planning

Erik Larsson (Linkoping University -- Sweden)
Invited talk 14:25 -- 15:00 Chair: Toshinori Hosokawa (Nihon University)

Power: The New Dimension of Test

Patrick Girard (LIRMM -- France)
Short break 15:00 -- 15:05
Panel 15:05 -- 16:15

Roads to Power-Safe LSI Testing

Organizer: K. Hatayama (Semiconductor Technology Academic Research Center -- Japan)

Moderator: X. Wen (Kyushu Institute of Technology -- Japan)

Panelists:
M. Tehranipoor (University of Connecticut -- USA)


S. Ravi (Texas Instruments India, Pvt. Ltd. -- India)


K. Ishibashi (Renesas Technology Corp. -- Japan)


K. Chakravadhanula (Cadence Design Systems, Inc. -- USA)


Coffee break 16:15 -- 16:35


Session 1 SoC testing 16:35 -- 18:00      Chair: Erik Larsson (Linkoping University)
1.1
Multicast Testing Method for NoC-based SoC Using Test Branches

Yinhe Han 1, #Wei Wang 2, Fang Fang 2, Jianbo Dong 1, Xiaowei Li 1, Shanlin Yang 2
(1 Chinese Academy of Sciences -- China, 2 Hefei University of Technology -- China)
1.2
A Reconfigurable Wrapper Design for Multi-Clock Domain Cores

#Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology -- Japan)
1.3
IEEE 1500-Based Delay Test Framework for At-Speed Testing of Multiple Clock Domains

#Po-Lin Chen, Tsin-Yuan Chang, Yu-Chieh Huang (National Tsing-Hua University -- Taiwan)
1.4
Constructing On-Chip Test Infra-Structure at Electronic System Level

Kuen-Jong Lee, #Chin-Yao Chang and Jia-Der Wang
(National Cheng Kung University -- Taiwan)


Banquet 18:45 -- 20:45  Century Royal Hotel ("Shinju no ma" on 20th floor)



November 28 (Friday)


Session 2 Power/Thermal aware testing 09:10 -- 10:10  
 Chair: Mohammad Tehranipoor (University of Connecticut)
2.1
Enabling Test Power Analysis at Register Transfer Level for Complex System on Chips

Ivano Midulla, #Chouki Aktouf (DeFacTo Technologies -- France)
2.2
On Reduction of Capture Power for Modular System-on-Chip Test

#Virendra Singh 1, Erik Larsson 2
(1 Indian Institute of Science -- India, 2 Linkoping University -- Sweden)
2.3
Wafer Level Burn-in Cost Reduction Using the Heat Generated by Test Patterns

Po-Lin Chen, #Hung-Chih Lin, Chih-Hu Wang, Wei-Ting Wang, Tsin-Yuan Chang
(National Tsing Hua University -- Taiwan)


Coffee break 10:10 -- 10:35


Session 3 High level & RTL testing (1) 10:35 -- 11:15
Chair: Kazumi Hatayama (Semiconductor Technology Academic Research Center)
3.1
Enhancement of Test Environment Generation for Assignment Decision Diagrams

Hideo Fujiwara 1, #Chia Yee Ooi 2, Yuki Shimizu 1 (1 Nara Institute of Science and Technology -- Japan, 2 University of Technology Malaysia -- Malaysia)
3.2
A New Class of Easily Testable Assignment Decision Diagram

#Norlina Paraman 1, Chia Yee Ooi 1, Ahmad Zuri Sha'ameri 1, Hideo Fujiwara 2 (1 University of Technology Malaysia -- Malaysia, 2 Nara Institute of Science and Technology -- Japan)
Short break 11:15 -- 11:20
Session 4 High level & RTL testing (2) 11:20 -- 12:30
Chair: Chouki Aktouf (DeFacTo Technologies)
4.1
RT-Level Identification of Potentially Testable Initialization Faults

Jaan Raik 1, Hideo Fujiwara 2, #Anna Krivenko 1 (1 Tallinn University of Technology -- Estonia, 2 Nara Institute of Science and Technology -- Japan)
4.2
An Approach to RTL-GL Path Mapping Based on Functional Equivalence

#Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (Nara Institute of Science and Technology -- Japan)
4.3
A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models

#Kazuya Sugiki 1, Toshinori Hosokawa 1, Masayoshi Yoshimura 2
(1 Nihon University -- Japan, 2 Kyushu University -- Japan)


Lunch 12:30 -- 14:00


Session 5 Reliability, Diagnosis & Debugging 14:00 -- 15:15
Chair: Masayuki Arai (Tokyo Metropolitan University)
5.1
Reliability and Performance of FPGA-Based Fault Tolerant Systems

#Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
(Hiroshima City University -- Japan)
5.2
Scan Chain Failure Diagnosis for Yield Improvement

#Gunaseelan Ponnuvel 1, Mark Grosset 2, Wu Yang 3, Yu Huang 3 (1 Nvidia Corporation -- USA, 2 Conexant System Inc. -- USA, 3 Mentor Graphics Corporation -- USA)
5.3
RTL Concurrent Error Detection using Modular Partitioning Technique

#Mohammad Hossein Sargolzaie, Mohammad Hashem Haghbayan, Saeed Safari
(University of Tehran -- Iran)
5.4
Experimental Studies on SMT-based Debugging

Andre Suelflow, #Goerschwin Fey, Rolf Drechsler (University of Bremen -- German)
Short break 15:15 -- 15:20
Session 6 Test data reduction 15:20 -- 16:10
Chair: Huawei Li (Chinese Academy of Sciences)
6.1
Scan Chain Configuration for BIST-aided Scan Test using Compatible Scan Flip-flops

#Masayuki Yamamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume
(The University of Tokushima -- Japan)
6.2
A Method for Test Data Reduction by Test Point Insertion Based on Necessary Assignment

#Hideyuki Ichihara, Kazuko Hiramoto, Yuki Yoshikawa, Tomoo Inoue
(Hiroshima City University -- Japan)
6.3
A Bit Flipping Reduction Method for Pseudo Random Patterns Using Don't Care Identification on BAST Architecture

#LingLing Wan 1, Motohiro Wakazono 1, Toshinori Hosokawa 1, Masayoshi Yoshimura 2 (1 Nihon University -- Japan, 2 Kyushu University -- Japan)


Coffee break 16:10 -- 16:30


Session 7 BIST & Delay testing 16:30 -- 17:30
Chair: Tsin-Yuan Chang (National Tsing Hua University)
7.1
Study on Hardware Overhead and Fault Location for Memory BIST

#Masayuki Arai 1, Tatsuro Endo 1, Kazuhiko Iwasaki 1, Michinobu Nakao 2, Iwao Suzuki 2 (1 Tokyo Metropolitan University -- Japan, 2 Renesas Technology Inc. -- Japan)
7.2
On Delay Calculation in 3-valued Fault Simulation

#Shinji Oku, Seiji Kajihara, Kohei Miyase, Xiaoqing Wen, Yasuo Sato (Kyushu Institute of Technology -- Japan)
7.3
How Many Paths Are Critical in Delay Testing

#Huawei Li, Xiang Fu, Yinghua Min, Xiaowei Li (Chinese Academy of Sciences -- China)


Closing session 17:30 -- 17:35









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